Octal EDGE-Triggered D-Type FLIP-FLOP
Description
SN64BCT374 OCTAL EDGEĆTRIGGERED DĆTYPE FLIPĆFLOP
WITH 3ĆSTATE OUTPUTS
SCBS066A − JUNE 1990 − REVISED NOVEMBER 1993
• State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• High-Impedance State During Power Up and
Power Down
• 3-State True Outputs Drive Bus Lines or
Buffer-Memory Address Registers
• Full Parallel Access for Loading • Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (N)
DW OR N PACKAGE (TOP VIEW)
OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the SN64BCT374 are edge-triggered D-type flip-flops.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output-enable (OE) does not affect the internal operations of the flip-flops.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The outputs are in a high-impedance state during power up and power down when the supply voltage is less than approximately 3 V.
The SN64BCT374 is characterized for operation from −ā 40°C to 85°C and 0°C to 70°C.
FUNCTION TABLE (ea...
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