3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
Description
SN54CDC586
3.
3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUPUTS
SGBS311A – FEBRUARY 1997 – REVISED JULY 2002
D Low Output Skew for Clock-Distribution
and Clock-Generation Applications
D Operates at 3.
3-V VCC D Distributes One Clock Input to 12 Outputs D Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double the Input Frequency
D No External RC Network Required D External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
D Application for Synchronous DRAM,
High-Speed Microprocessor
D TTL-Compatible Inputs and Outputs D Outputs Drive Parallel 50-Ω Terminated
Transmission Lines
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D Distributed VCC and Ground Pins Reduce
Switching Noise
D Packaged in 56-Pin Ceramic Flat Package
description
The SN54CDC586 is a high-performance, low-skew, low-jitter clock driver.
It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal.
It is specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz, or down to 25 MHz on outputs configured as half-frequency outputs.
The SN54CDC586
Woperates at 3.
3-V VCC and is designed to drive a
properly terminated 50- transmission line.
WD PACKAGE (TOP VIEW)
NC AVCC AGND FBIN AGND SEL0 SEL1 GND GND
1Y1 VCC GND 1Y2 VCC GND 1Y3 VCC GND GND 2Y1 VCC GND 2Y2 VCC GND 2Y3 VCC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 NC
55 CLKIN
54 NC
53 AVCC 52 OE
51 TEST
50 CLR
49 VCC 48 4Y3
47 GND
46 VCC 45 4Y2 44 GND 43 VCC 42 4Y1 41 GND 40 GND 39 VCC 38 3Y3 37 GND 36 VCC 35 3Y2 34 GND 33 VCC 32 3Y1 31 GND 30 GND 29 NC
NC – No internal connection
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to CLKIN.
One of the 12 output clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input and the output...
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