OCTAL BUFFER/LINE DRIVER
Description
74AC11240
OCTAL BUFFER/LINE DRIVER
WITH 3-STATE OUTPUTS
SCAS448A – MAY 1987 – REVISED APRIL 1996
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (DW) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (NT)
description
DB, DW, OR NT PACKAGE (TOP VIEW)
1Y1 1Y2 1Y3 1Y4 GND GND GND GND 2Y1 2Y2 2Y3 2Y4
1 2 3 4 5 6 7 8 9 10 11 12
24 1OE
23 1A1
22 1A2
21 1A3
20 1A4 19 VCC 18 VCC 17 2A1 16 2A2 15 2A3 14 2A4 13 2OE
This octal buffer/line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device provides inverting outputs and symmetrical active-low output-enable (OE) inputs.
This device features high fan-out and improved fan-in.
The 74AC11240 is organized as two 4-bit buffers/line drivers with separate OE inputs.
When OE is low, the device passes inverted data from the A inputs to the Y outputs.
When OE is high, the outputs are in the high-impedance state.
The 74AC11240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE (each buffer)
INPUTS OE A
OUTPUT Y
LH
L
LL
H
HX
Z
logic symbol†
1OE
1A1 1A2 1A3 1A4
24
23 22 21 20
EN 1
1 1Y1
2 1Y2
3 1Y3
4 1Y4
2OE
2A1 2A2 2A3 2A4
13
17 16 15 14
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EN 1
9 2Y1
10 2Y2
11 2Y3
12 2Y4
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EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
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