3-Line To 8-Line Decoder/Demultiplexer
Description
74AC11138 3ĆLINE TO 8ĆLINE DECODER/DEMULTIPLEXER
D Designed Specifically for High-Speed
Memory Decoders and Data Transmission Systems
D Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)
SCAS042B − MAY 1988 − REVISED APRIL 1996
D, N, OR PW PACKAGE (TOP VIEW)
Y1 Y2 Y3 GND Y4 Y5 Y6 Y7
1 2 3 4 5 6 7 8
16 Y0 15 A 14 B 13 C 12 VCC 11 G1 10 G2A 9 G2B
description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.
In high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory.
This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of eight output lines.
Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
XHXXXXHHHHHHHH
XXHXXXHHHHHHHH
L XXXXXHHHHHHHH
HL L L L L LHHHHHHH
HL L L LHHLHHHHHH
HL L LHLHHLHHHHH
HL L LHHHHHLHHHH
HL LHL LHHHHLHHH
HL LHLHHHHH...
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