QUADRUPLE 2-INPUT POSITIVE-OR GATE
Description
74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic
300-mil DIPs (N)
SCAS007C – JULY 1987 – REVISED APRIL 1996
D, DB, OR N PACKAGE (TOP VIEW)
1A 1Y 2Y GND GND 3Y 4Y 4B
1 2 3 4 5 6 7 8
16 1B 15 2A 14 2B 13 VCC 12 VCC 11 3A 10 3B
9 4A
description
This device contains four independent 2-input OR gates.
It performs the Boolean function
+ ) +Y A B or Y A • B in positive logic.
The 74AC11032 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE (each gate)
INPUTS AB
OUTPUT Y
HX
H
XH
H
LL
L
logic symbol†
1 1A
16 1B
15 2A
14 2B
11 3A
10 3B
9 4A
8 4B
≥1
2 1Y
3 2Y
6 3Y
7 4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
logic diagram (positive logic)
1A 1 1B 16
2A 15 2B 14
3A 11 3B 10
4A 9 4B 8
2 1Y 3
2Y 6
3Y 7
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC .
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