8-Input Positive-NAND Gates
Description
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• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
description
These devices contain a single 8-input NAND gate and perform the following Boolean functions in positive logic:
Y = A • B • C • D • E • F • G • H or Y=A+B+C+D+E+F+G+H
The 54AC11030 is characterized for operation over the full military temperature range of − 55°C to 125°C.
The 74AC11030 is characterized for operation from −40°C to 85°C.
AE
NC NC
Y NC
54AC11030, 74AC11030 8ĆINPUT POSITIVEĆNAND GATES
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SCAS001A − JUNE 1987 − REVISED APRIL 1993
54AC11030 .
.
.
J PACKAGE 74AC11030 .
.
.
D OR N PACKAGE
(TOP VIEW)
C B A GND Y NC NC
1 2 3 4 5 6 7
14 D 13 E 12 F 11 VCC 10 NC 9G 8H
54AC11030 .
.
.
FK PACKAGE (TOP VIEW)
VCC NC
3 2 1 20 19
D4
18 G
NC 5
17 NC
C6
16 H
NC 7
15 NC
B8
14 NC
9 10 11 12 13
GND F
FUNCTION TABLE
INPUTS A THRU H
OUTPUT Y
All inputs H
L
One or more inputs L
H
NC − No internal connection
logic symbol†
3 A
2 B
1 C
14 D
13 E
12 F
9 G
8 H
&
5 Y
logic diagram (positive logic)
3 A
2 B
1 C
14 D
13 E
12 F
9 G
8 H
5 Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265 •POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
Copyright 1993, Texas Instruments Incorporated 2−1
54AC11030, 74AC11030 8ĆINPUT POSITIVEĆNAND GATES ą
SCAS001A − JUNE 1987 − REVISED APRIL 1993
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