SmartFusion Customizable System-on-Chip
Description
Revision 14
SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS) • Hard 100 MHz 32-bit ARM® Cortex®-M3 Processor
– 1.
25 DMIPS/MHz Throughput from Zero Wait State Memory
– Memory Protection Unit (MPU) – Single Cycle Multiplication, Hardware Divide – JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces • Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128 Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, Implemented in 2 Physical Blocks to Enable Simultaneous Access from 2 Different Masters
• Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory Bandwidth,1 Allowing Multi-Master Schemes
• 10/100 Ethernet MAC with RMII Interface2
• Programmable External Memory Controller, Which Supports:
– Asynchronous Memories – NOR Flash, SRAM, PSRAM – Synchronous SRAMs • Two I2C Peripherals
• Two 16550 Compatible UARTs
• Two SP...
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