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ICS542

CLOCK DIVIDER

ICS542 PDF File

Description

CLOCK DIVIDER DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input.
The chip accepts a clock input up to 156 MHz at 3.
3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock.
There are two outputs on the chip, one being a low-skew divide by two of the other.
For instance, if an 100 MHz input clock is used, the ICS542 can produce low-skew 50 MHz and 25 MHz clocks, or low skew 25 MHz and 12.
5 MHz clocks.
The chip has an all-chip power-down mode that stops the outputs low, and an OE pin that tri-states the outputs.
See the ICS541 and ICS543 for other clock dividers, and the ICS501, 502, 511, 512, and 525 for clock multipliers.
Features • 8-pin SOIC package, Pb free • Available in RoHS compliant package • IDT’s lowest cost clock divider • Low skew (500 ps) outputs.
One is /2 of the other • Easy to use with other generators and buffers • Input clock frequency up to 156 MHz • Output cl...

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