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GS81302R18E

GSI Technology

144Mb SigmaDDR-II Burst of 4 SRAM


GS81302R18E
GS81302R18E

PDF File GS81302R18E PDF File


Description
GS81302R08/09/18/36E-375/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II Burst of 4 SRAM 375 MHz–250 MHz 1.
8 V VDD 1.
8 V and 1.
5 V I/O Features • Simultaneous Read and Write SigmaDDR™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.
8 V +100/–100 mV core power supply • 1.
5 V or 1.
8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
1 JTAG-compliant Boundary Scan • Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available SigmaDDR™ Family Overview The GS81302R08/09/18/36E are built in compliance with the SigmaDDR-II SRAM pinout standard for Common I/O synchronous SRAMs.
They are 150,994,944-bit (144Mb) SRAMs.
The GS81302R08/09/18/36E SigmaDDR-II SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
Clocking and Addressing Schemes The GS81302R08/09/18/36E SigmaDDR-II SRAMs are synchronous devices.
They employ two input register clock inputs, K and K.
K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer.
The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs.
C and C are also independent single-ended clock inputs, not differential inputs.
If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.
Each internal read and write operation in a SigmaDDR-II B4 RAM is four times wider than the device I/O bus.
An input data bus de-multiplexer is used to accumulate incoming data ...



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