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CR16MES5 Dataheets PDF



Part Number CR16MES5
Manufacturers National Semiconductor
Logo National Semiconductor
Description Family of CompactRISC 16-Bit Microcontrollers
Datasheet CR16MES5 DatasheetCR16MES5 Datasheet (PDF)

CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/ CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers December 2001 CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers 1.0 General Description The family of CompactRISC 16-bit microcontrollers offer the high performance of a RISC architecture while retaining the advantages of a traditional Complex Instruc.

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CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/ CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers December 2001 CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers 1.0 General Description The family of CompactRISC 16-bit microcontrollers offer the high performance of a RISC architecture while retaining the advantages of a traditional Complex Instruction Set Computer (CISC): compact code, on-chip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 20 million instructions per second (MIPS) at a clock rate of 20 MHz. The family of CompactRISC™ microcontrollers are general-purpose 16-bit microcontrollers based on a Reduced Instruction Set Computer (RISC) architecture. The device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption, resulting in decreased system cost. Block Diagram Fast Osc Slow Osc CR16B Core Processing Unit Clock Generator Power-on-Reset Core Bus Peripheral Bus Controller 48k Flash Program Memory 2 kbyte RAM 640 Bytes EEPROM Data Memory boot ROM Interrupt Power-Save Control Management (ICU) WATCHDOG Peripheral Bus I/O µWire/SPI Two USARTs Two MFTs A/D MIWU Two Analog Comparators Real-Time Timer Please note that not all family members contain same peripheral modules and features. TRI-STATE® is a registered trademark of National Semiconductor Corporation. ©2001 National Semiconductor Corporation www.national.com Table of Contents 1.0 2.0 3.0 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 CR16B CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.6 Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.7 Dual Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 6 3.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.9 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 6 3.10 Real-Time TIMER and Watchdog . . . . . . . . . . . . . . 6 3.11 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.12 MICROWIRE/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.13 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.14 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . 7 3.15 Development Support . . . . . . . . . . . . . . . . . . . . . . . 7 3.16 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 ENV0 and ENV1 Pins . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Module Configuration (MCFG) Register . . . . . . . . 12 4.3 Module Status (MSTAT) Register . . . . . . . . . . . . . 12 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . 14 CPU and Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 General-Purpose Registers . . . . . . . . . . . . . . . . . . 15 6.2 Dedicated Address Registers . . . . . . . . . . . . . . . . 15 6.3 Processor Status Register . . . . . . . . . . . . . . . . . . . 15 6.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . 16 6.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.6 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.7 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . 18 7.3 Wait and Hold States Used . . . . . . . . . . . . . . . . . . 19 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . 21 8.2 RAM Memory. . . . . . . . . . . . . . . .


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