IS45S32400B

IS45S32400B 4Meg x 32 128-MBIT SYNCHRONOUS DRAM ISSI® JULY 2006 FEATURES Clock frequency: 166, 143, 125, 100 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Power supply IS45S32400B VDD VDDQ 3.3V 3.3V LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh with programmable refresh periods 4096 refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Automotive Temperature Range Option A: 0oC to +70oC Option A1: -40oC to +85oC Available in 86-pin TSOP-II and 90-ball FBGA Available in Lead-free OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 67 8 10 166 143 125 100 5.4 5.4 6.5 6.5 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this sp...