SYNCHRONOUS DYNAMIC RAM
IS42S32200E IS45S32200E
512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
AUGUST 2009
FEATURES
• Clock...
Description
IS42S32200E IS45S32200E
512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
AUGUST 2009
FEATURES
Clock frequency: 200, 166, 143, 133 MHz
Fully synchronous; all signals referenced to a positive clock edge
Internal bank for hiding row access/precharge
Single 3.3V power supply
LVTTL interface
Programmable burst length: (1, 2, 4, 8, full page)
Programmable burst sequence: Sequential/Interleave
Self refresh modes
4096 refresh cycles every 16ms (A2 grade) or 64ms (Commercia, Industrial, A1 grade)
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42/45S32200E is
organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve highspeed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time CAS Latency = 3 CAS Latency = 2
Clk Frequency CAS Latency = 3 CAS Latency = 2
Access Time from Clock CAS Latency = 3 CAS Latency = 2
-5 -6
5 6 10 10
200 166 100 100
5 5.5 8 8
-7 -75E Unit
7 – 10 7.5
ns ns
143 – Mhz
100 133 Mhz
5.5 – 8 5.5
ns ns
OPTIONS
Packages: 86-pin TSOP-II 90-ball TF-BGA
Operating temperature range:
Commerc...
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