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R5F521A6BDFP Dataheets PDF



Part Number R5F521A6BDFP
Manufacturers Renesas
Logo Renesas
Description MCUs
Datasheet R5F521A6BDFP DatasheetR5F521A6BDFP Datasheet (PDF)

Datasheet RX21A Group Renesas MCUs 50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ∆Σ A/D Converter, up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC, MPC, RTC; up to 9 comms interfaces R01DS0129EJ0110 Rev.1.10 Aug 28, 2014 Features ■ 32-bit RX CPU core  Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operati.

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Datasheet RX21A Group Renesas MCUs 50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit ∆Σ A/D Converter, up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC, MPC, RTC; up to 9 comms interfaces R01DS0129EJ0110 Rev.1.10 Aug 28, 2014 Features ■ 32-bit RX CPU core  Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  Memory protection unit  On-chip debugging circuit ■ Low power design and architecture  Operation from a single 1.8-V to 3.6-V supply (2.7 V to 3.6 V for the ΔΣ A/D converter operating voltage)  Deep software standby mode with RTC remaining usable  Four low power modes ■ 24-bit ∆Σ A/D Converter  SNDR = 85dB  Seven ΔΣ converter units available. Seven channels can be operated simultaneously or independently.  Up to x 64 PGA gain for differential input ■ On-chip flash memory for code, no wait states  50-MHz operation, 20-ns read cycle  No wait states for reading at full CPU speed  256-K to 512-Kbyte capacities  User code programmable via the SCI  Programmable at 1.8 V  For instructions and operands ■ On-chip data flash memory  8 Kbytes (Number of times of reprogramming: 100,000)  Erasing and programming impose no load on the CPU. ■ On-chip SRAM, no wait states  32-K to 64-Kbyte size capacities ■ DMA  DMAC: Incorporates four channels  DTC: Four transfer modes ■ Reset and supply management  Nine types of reset, including the power-on reset (POR)  Low voltage detection (LVD) with voltage settings ■ Clock functions  Frequency of external clock: Up to 20 MHz  Frequency of the oscillator for sub-clock generation: 32.768 kHz  PLL circuit input: 4 MHz to 12.5 MHz  On-chip low- and high-speed oscillators, dedicated onchip low-speed oscillator for the IWDT  Generation of a dedicated 32.768-kHz clock for the RTC  Clock frequency accuracy measurement circuit (CAC) ■ Real-time clock  Adjustment functions (30 seconds, leap year, and error)  Year and month display or 32-bit second display (binary counter) is selectable  Time capture on event-signal input through external pins  RTC capable of initiating return from deep software standby mode PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch PTLG0100JA-A 7×7mm, 0.65-mm pitch ■ Independent watchdog timer  125-kHz on-chip oscillator produces a dedicated clock signal to drive IWDT operation. ■ Useful functions for IEC60730 compliance  Self-diagnostic and disconnection-detection assistance functions for the A/D converter, clock-frequency accuracy-measurement circuit, independent watchdog timer, functions to assist in RAM testing, etc. ■ Up to nine communications channels  SCI with many useful functions (up to five channels) Asynchronous mode, clock synchronous mode, smart card interface  IrDA Interface (one channel, in cooperation with the SCI5)  I2C bus interface: Transfer at up to 400 kbps, capable of SMBus operation (two channels)  RSPI (two channels) ■ Up to 14 extended-function timers  16-bit MTU: input capture, output compare, complementary PWM output, phase counting mode (six channels)  8-bit TMR (four channels)  16-bit compare-match timers (four channels) ■ 10-bit A/D converter  Conversion time 2.0 μs  Self-diagnostic function and analog input disconnection detection assistance function ■ 10-bit D/A converter ■ Analog comparator ■ General I/O ports  5-V tolerant, open drain, input pull-up, switching of driving ability ■ MPC  Multiple locations are selectable for I/O pins of peripheral functions ■ ELC  Module operation can be initiated by event signals without going through interrupts.  Modules can operate while the CPU is sleeping. ■ DEU  Encryption and decryption of AES  128-, 192-, or 256-bit key length  ECB/CBC Mode ■ Temperature sensor ■ Operating temp. range  40C to +85C  40C to +105C R01DS0129EJ0110 Rev.1.10 Aug 28, 2014 Page 1 of 132 RX21A Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 shows the outline of the specifications and Table 1.2 shows the comparison of the functions of products in different packages. Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1 / 4) Classification Module/Function Description CPU CPU  Maximum operating frequency: 50 MHz  32-bit RX CPU  Minimum instruction execution time: One instruction per state (cycle of the system clock)  Address space: 4-Gbyte linear  Register set General purpose: Sixteen 32-bit r.


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