Document
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A
256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM
JANUARY 2014
FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and
control • Burst sequence control using MODE input • Three chip enable option for simple depth ex-
pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for BGA package • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% • JEDEC 100-Pin QFP, 119-ball BGA, and 165-
ball BGA packages • Lead-free available
FAST ACCESS TIME
Symbol Parameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
DESCRIPTION
The ISSI IS61LPS/VPS25636A, IS61LPS25632A,
IS64LPS25636A and IS61LPS/VPS51218A are highspeed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS/ VPS25636A and IS64LPS25636A are organized as 262,144 words by 36 bits. The IS61LPS25632A is organized as 262,144 words by 32 bits. The IS61LPS/ VPS51218A is organized as 524,288 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
250 200 166 2.6 3.1 3.5 4 5 6 250 200 166
Units ns ns MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. 1
Rev. M 01/14/14
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A
BLOCK DIAGRAM
CLK
ADV ADSC ADSP
A
18/19
MODE
CLK
Q0
BINARY COUNTER
CE Q1
A0 A1
CLR
A0' A1'
DQ ADDRESS REGISTER CE
CLK
16/17
256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY
18/19
32, 36, or 18
32, 36, or 18
GW BWE
BW(a-d) x18: a,b x32/x36: a-d
D DQ(a-d) Q BYTE WRITE REGISTERS
CLK
CE CE2 CE2
ZZ OE
2
POWER DOWN
DQ ENABLE
REGISTER CE
CLK
DQ ENABLE DELAY
REGISTER CLK
2/4/8 INPUT
REGISTERS CLK
OUTPUT REGISTERS
CLK
32, 36, or 18
DQa - DQd OE
Integrated Silicon Solution, Inc.
Rev. M 01/14/14
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A
165-pin BGA
165-Ball, 13x15 mm BGA
119-pin BGA
119-Ball, 14x22 mm BGA
Bottom view
Bottom View
Integrated Silicon Solution, Inc.
Rev. M 01/14/14
3
IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A
119 BGA PACKAGE PIN CONFIGURATION-256K x 36 (TOP VIEW)
12
3
4
5
67
A VDDQ
A
A ADSP A
B NC CE2
A ADSC
A
A VDDQ A NC
C NC
A
A VDD A
A NC
D DQc DQPc Vss NC Vss DQPb DQb
E DQc DQc Vss
CE
Vss
DQb
DQb
F
VDDQ
DQc
Vss
G DQc DQc BWc
OE ADV
Vss BWb
DQb DQb
VDDQ DQb
H DQc DQc
Vss
GW
Vss
DQb
DQb
J
VDDQ
VDD
K DQd DQd
NC Vss
VDD CLK
NC
VDD
VDDQ
Vss
DQa
DQa
L DQd DQd BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
Vss
BWE
N DQd DQd
Vss
A1*
P DQd DQPd Vss
A0*
R NC
A
MODE
VDD
T NC NC
A
A
Vss
DQa
VDDQ
Vss
DQa
DQa
Vss DQPa DQa
NC A NC
A NC ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A
Pin Name Address Inputs
A0, A1
Synchronous Burst Address Inputs
A.