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uPD46185184B Dataheets PDF



Part Number uPD46185184B
Manufacturers Renesas
Logo Renesas
Description 18M-BIT QDR II SRAM 4-WORD BURST OPERATION
Datasheet uPD46185184B DatasheetuPD46185184B Datasheet (PDF)

μPD46185084B μPD46185094B μPD46185184B μPD46185364B Datasheet 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION Description R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46185084B, μPD46185.

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μPD46185084B μPD46185094B μPD46185184B μPD46185364B Datasheet 18M-BIT QDRTM II SRAM 4-WORD BURST OPERATION Description R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364B is a 524,288-word by 36-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46185084B, μPD46185094B, μPD46185184B and μPD46185364B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA. Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (13 x 15) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation • Four-tick burst for reduced address frequency • Two input clocks (K and K#) for precise DDR timing at clock rising edges only • Two output clocks (C and C#) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed. • User programmable impedance output (35 to 70 Ω) • Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz) • Simple control logic for easy depth expansion • JTAG 1149.1 compatible test access port R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 Page 1 of 38 μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B Ordering Information Part No. μPD46185084BF1-E33-EQ1-A μPD46185084BF1-E40-EQ1-A μPD46185094BF1-E33-EQ1-A μPD46185094BF1-E40-EQ1-A μPD46185184BF1-E33-EQ1-A μPD46185184BF1-E40-EQ1-A μPD46185364BF1-E33-EQ1-A μPD46185364BF1-E40-EQ1-A μPD46185084BF1-E33Y-EQ1-A μPD46185084BF1-E40Y-EQ1-A μPD46185094BF1-E33Y-EQ1-A μPD46185094BF1-E40Y-EQ1-A μPD46185184BF1-E33Y-EQ1-A μPD46185184BF1-E40Y-EQ1-A μPD46185364BF1-E33Y-EQ1-A μPD46185364BF1-E40Y-EQ1-A μPD46185084BF1-E33-EQ1 μPD46185084BF1-E40-EQ1 μPD46185094BF1-E33-EQ1 μPD46185094BF1-E40-EQ1 μPD46185184BF1-E33-EQ1 μPD46185184BF1-E40-EQ1 μPD46185364BF1-E33-EQ1 μPD46185364BF1-E40-EQ1 μPD46185084BF1-E33Y-EQ1 μPD46185084BF1-E40Y-EQ1 μPD46185094BF1-E33Y-EQ1 μPD46185094BF1-E40Y-EQ1 μPD46185184BF1-E33Y-EQ1 μPD46185184BF1-E40Y-EQ1 μPD46185364BF1-E33Y-EQ1 μPD46185364BF1-E40Y-EQ1 Organization (word x bit) 2M x 8 2M x 9 1M x 18 512K x 36 2M x 8 2M x 9 1M x 18 512K x 36 2M x 8 2M x 9 1M x 18 512K x 36 2M x 8 2M x 9 1M x 18 512K x 36 Cycle time 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns 3.3ns 4.0ns Clock frequency 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz 300MHz 250MHz Core Supply Voltage 1.8 ± 0.1 V 1.8 ± 0.1 V 1.8 ± 0.1 V 1.8 ± 0.1 V Operating Ambient Temperature TA = 0 to 70°C TA = −40 to 85°C TA = 0 to 70°C TA = −40 to 85°C Package 165-pin PLASTIC BGA (13 x 15) Lead-free 165-pin PLASTIC BGA (13 x 15) Lead R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 Page 2 of 38 μPD46185084B, μPD46185094B, μPD46185184B, μPD46185364B Pin Arrangement 123 A CQ# VSS/72M A B NC NC NC C NC NC NC D NC D4 NC E NC NC Q4 F NC NC NC G NC D5 Q5 H DLL# VREF VDDQ J NC NC NC K NC NC NC L NC Q6 D6 M NC NC NC N NC D7 NC P NC NC Q7 R TDO TCK A 165-pin PLASTIC BGA (13 x 15) (Top View) [μPD46185084B] 2M x 8 45678 W# NW1# K# NC/144M R# A NC/288M K NW0# A VSS A NC A VSS VSS VSS VSS VSS VSS VDDQ VSS VSS VSS VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VSS VSS VSS VDDQ VSS VSS VSS VSS VSS VSS A A A VSS AACAA A A C# A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 VSS/36M NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI A D0 to D7 Q0 to Q7 R# W# NW0#, NW1# K, K# C, C# CQ, CQ# ZQ DLL# : Address inputs : Data inputs : Data outputs : Read input : Write input : Nibble Write data select : Input clock : Output clock : Echo clock : Output impedance matching : PLL disable TMS TDI TCK TDO VREF VDD VDDQ VSS NC NC/xxM : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : Ground : No connection : Expansion address for xxMb Remarks 1. ×××# indicates active L.


uPD46185094B uPD46185184B uPD46185364B


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