M5M5V5636UG-16

DESCRIPTION The M5M5V5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Renesas's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5V5636UG operates on 3.3V power/ 2.5V I/O supply or a single 3.3V power supply and are 3.3V CMOS compatible. The M5M5V5636UG also operates on a single 2.5V power supply and is also 2.5V CMOS compatible. Therefore the M5M5V5636UG can replace the M5M5T5636UG. The M5M5V5636UG-16 operates at 167MHz or 133MHz and is guaranteed both AC DC electrical characteristics of 167MHz and those of 133MHz. FEATURES Fully registered inputs and outputs for pipelined operation Fast clock speed: 167 and 133 MHz Fast access time: 3.8 and 4.2 ns Single 3.3V -5% and +5% power supply VDD Separate VDDQ for 3.3V or 2.5V I/O Single 2.5V -5% and +5% power supply VDD Individual byte write (BWa# - BWd#) controls may be tied LOW Single Read/Write control pin (W#) CKE# pin to enable clock and suspend operations Internally self-timed, registers outputs eliminate the need to control G# Snooze mode (ZZ) for power down Linear or Interleaved Burst Modes Three chip enables for simple depth expansion JTAG boundary scan support Renesas LSIs M5M5V5636UG – 16 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM PACKAGE 165(11x15) bump BGA Body Size (13mm x 15m...