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HM62A16100I Dataheets PDF



Part Number HM62A16100I
Manufacturers Renesas
Logo Renesas
Description 16M SRAM
Datasheet HM62A16100I DatasheetHM62A16100I Datasheet (PDF)

HM62A16100I Series Wide Temperature Range Version 16 M SRAM (1-Mword × 16-bit) REJ03C0053-0001Z Preliminary Rev. 0.01 Jun.02.2003 Description The Renesas HM62A16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62A16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the pac.

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HM62A16100I Series Wide Temperature Range Version 16 M SRAM (1-Mword × 16-bit) REJ03C0053-0001Z Preliminary Rev. 0.01 Jun.02.2003 Description The Renesas HM62A16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62A16100I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75 mm bump pitch for high density surface mounting. Features • Single 1.8 V supply: 1.65 V to 2.2 V • Fast access time: 70 ns (max) • Power dissipation:  Active: 3.6 mW/MHz (typ)  Standby: 0.9 µW (typ) • Completely static memory.  No clock or timing strobe required • Equal access and cycle times • Common data input and output.  Three state output • Battery backup operation.  2 chip selection for battery backup • Temperature range: −40 to +85°C Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Renesas Technology’s Sales Dept. regarding specification. Rev.0.01, Jun.02.2003, page 1 of 17 HM62A16100I Series Ordering Information Type No. HM62A16100LBPI-7 HM62A16100LBPI-7SL Access time 70 ns 70 ns Package 48-bump CSP with 0.75 mm bump pitch (TBP-48F) Rev.0.01, Jun.02.2003, page 2 of 17 HM62A16100I Series Pin Arrangement 48-bumps CSP 1 23456 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 A17 A7 I/O3 VCC E VCC I/O12 VSS A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NU (Top view) Pin Description Pin name Function A0 to A19 Address input I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2 WE Write enable OE Output enable LB Lower byte select UB Upper byte select VCC V SS NU*1 Power supply Ground Not used (test mode pin) Note: 1. This pin should be connected to a ground (V ), or not be connected (open). SS Rev.0.01, Jun.02.2003, page 3 of 17 HM62A16100I Series Block Diagram LSB A19 A8 A9 A10 A11 A12 A13 A14 A16 A18 A15 A3 MSB A6 I/O0 I/O15 CS2 CS1 LB UB WE OE Row decoder • • • • • Memory matrix 8,192 x 128 x 16 V CC V SS Input data control • • Column I/O Column decoder • • MSBA17 A7 A5 A4 A2 A1 A0 LSB •• Control logic Rev.0.01, Jun.02.2003, page 4 of 17 HM62A16100I Series Operation Table CS1 CS2 WE OE UB LB I/O0 to I/O7 H × × × × × High-Z × L × × × × High-Z × × × × H H High-Z L H H L L L Dout L H H L H L Dout L H H L L H High-Z L H L × L L Din L H L × H L Din L H L × L H High-Z L H H H × × High-Z Note: H: VIH, L: VIL, ×: VIH or VIL I/O8 to I/O15 High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z Operation Standby Standby Standby Read Lower byte read Upper byte read Write Lower byte write Upper byte write Output disable Absolute Maximum Ratings Parameter Symbol Power supply voltage relative.


ES1M HM62A16100I LDTC123TKT1G


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