HD74ALVC2G125

HD74ALVC2G125 Dual Bus Buffer with 3-state Output REJ03D0171–0200Z (Previous ADE-205-621A (Z)) Rev.2.00 Dec.18.2003 Description The HD74ALVC2G125 has dual bus buffer with 3-state output in an 8 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features The basic gate function is lined up as Renesas uni logic series. Supplied on emboss taping for high-speed automatic mounting. Supply voltage range : 1.2 to 3.6 V Operating temperature range: −40 to +85°C All inputs VIH (Max.) = 3.6 V (@VCC = 0 V to 3.6 V) All outputs VO (Max.) = 3.6 V (@VCC = 0 V) Output current ±2 mA (@VCC = 1.2 V) ±4 mA (@VCC = 1.4 V to 1.6 V) ±6 mA (@VCC = 1.65 V to 1.95 V) ±18 mA (@VCC = 2.3 V to 2.7 V) ±24 mA (@VCC = 3.0 V to 3.6 V) Ordering Information Part Name Package Type Package Code Package Abbreviation HD74ALVC2G125USE SSOP-8 pin TTP-8DBV US Taping Abbreviation (Quantity) E (3,000 pcs/reel) Rev.2.00, Dec.18.2003, page 1 of 12 HD74ALVC2G125 Outline and Article Indication HD74ALVC2G125 Index band Lot No. SSOP-8 Function Table Inputs OE L L H H: ...