SI53308

Si53308 DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR Features  6 differential or 12 (in phase)  Loss of signal (LOS) monitors for LVCMOS outputs loss of input clock  Ultra-low additive jitter: 45 fs rms  Independent VDD and VDDO :  Wide frequency range: 1 to 725 MHz 1.8/2.5/3.3 V  Any-format input with pin selectable  Selectable LVCMOS drive strength to output formats: LVPECL, low power tailor jitter and EMI performance LVPECL, LVDS, CML, HCSL, LVCMOS  Synchronous output enable  Output clock division: /1, /2, /4  Low output-output skew: 25 ps  Small size: 32-QFN (5 mm x 5 mm)  RoHS compliant, Pb-free  Industrial temperature range: –40 to +85 °C Applications  High-speed clock distribution  Ethernet switch/router  Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Description The Si53308 is an ultra low jitter six output differential buffer with pin-selectable output clock signal format and divider selection. The device is a dual 1:3 buffer providing the functionality of two independent buffers in a single IC. The Si53308 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53308 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core ...