SI53106

Si53106 SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER Features  Six 0.7 V low-power, push-pull,  Low phase jitter (Intel QPI, PCIe HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock outputs compliant  Individual OE HW pins for each  Gen 3 SRNS Compliant output clock  PLL or bypass mode  100 MHz /133 MHz PLL  Spread spectrum tolerable  operation, supports PCIe and QPI PLL bandwidth SW SMBUS programming overrides the latch    value from HW pin 1.05 to 3.3 V I/O supply voltage 50 ps output-to-output skew Industrial Temperature: –40 to 85 °C  SMBus address configurable to allow multiple buffers in a single   40-pin QFN For higher output devices or control network 3.3 V supply variations of this device, contact voltage operation Silicon Labs Ordering Information: See page 29. Patents pending Applications  Server  Storage  Datacenter  Enterprise Switches and Routers Description The Si53106 is a low-power, 6-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock...