CY7C1399

CY7C1399 Features Single 3.3V power supply Ideal for low-voltage cache memory applications High speed — 12/15 ns Low active power — 255 mW (max.) Low CMOS standby power (L) — 180 µW (max.), f=fMAX 2.0V data retention (L) — 40 µW Low-power alpha immune 6T cell Plastic SOJ and TSOP packaging Functional Description The CY7C1399 is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion Logic Block Diagram A0 A1 A2 AA34 A5 A6 AA78 A9 CE WE OE ROW DECODER SENSE AMPS INPUT BUFFER 32K x 8 ARRAY COLUMN DECODER POWER DOWN 32K x 8 3.3V Static RAM is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected. An active LOW Write Enable signal (WE) controls the writing/ reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, ou...