Document
IFX30081SJV
50mA, Adjustable Linear Voltage Regulator with Ultra Low Quiescent Current
Data Sheet
Rev. 1.0, 2015-02-04
Standard Power
50mA, Adjustable Linear Voltage Regulator with Ultra Low Quiescent Current
IFX30081SJV
1 Overview
Features • Ultra Low Current Consumption of typ. 5 µA • Wide Input Voltage Range of 2.75 V to 42 V • Output Current Capability up to 50 mA • Shutdown Current less than 1 µA • Low Drop Out Voltage of typ. 100mV @ 50mA • Output Current Limit Protection • Overtemperature Shutdown • Enable Feature • Available in PG-DSO-8
• Wide Temperature Range -40°C ≤ Tj ≤ 125°C
• Green Product (RoHS compliant)
Applications • Battery Operated Systems • Sensor Supplies • Smoke and Fire Detectors
PG-DSO-8
The IFX30081SJV is not qualified and manufactured according to the requirements of Infineon Technologies with regards to automotive and/or transportation applications. For automotive applications please refer to the Infineon TLx (TLE, TLS, TLF...) voltage regulator products.
Description
The IFX30081SJV is a wide input voltage, low drop out voltage and ultra low quiescent current linear voltage regulator.
With a wide input voltage range of 2.75 V to 42 V and ultra low current consumption of only 5 µA this regulator is perfectly suitable for battery operated systems as well as supplies for sensors.
The IFX30081SJV is available with an adjustable output voltage with an accuracy of 2 % and maximum output current up to 50 mA.
The regulation concept implemented in the IFX30081SJV combines fast regulation and very good stability while requiring only a small ceramic capacitor of 1 μF at the output. Internal protection features like output current
Type IFX30081SJV
Data Sheet
Package PG-DSO-8
2
Marking 30081SJV
Rev. 1.0, 2015-02-04
IFX30081SJV
Overview
limitation and overtemperature shutdown are implemented to protect the device against failures like output short circuit to GND, over-current and over-temperature. The device can be switched on and off by the Enable feature. When the device is switched off, the current consumption is less than 1 µA.
Choosing External Components
An input capacitor CIN is recommended to compensate line influences. The output capacitor COUT is necessary for the stability of the regulating circuit. Stability is guaranteed at values COUT ≥ 1µF and an ESR ≤ 100 Ω within the
whole operating range.
Data Sheet
3 Rev. 1.0, 2015-02-04
2 Block Diagram
IFX30081SJV
Block Diagram
IN
Current Limitation EN
Enable
Temperature Shutdown
OUT
ADJ Bandgap Reference
GND
Figure 1 Block Diagram IFX30081SJV
Data Sheet
4 Rev. 1.0, 2015-02-04
3 Pin Configuration
3.1 Pin Assignment in PG-DSO-8 Package
IFX30081SJV
Pin Configuration
IN N.C.
EN GND
1 2 3 4
8 OUT 7 ADJ 6 N.C. 5 N.C.
Figure 2 Pin Configuration IFX30081SJV in PG-DSO-8 package
3.2 Pin Definitions and Functions in PG-DSO-8 Package
Pin Symbol 1 IN
2 N.C. 3 EN
4 GND 5 N.C. 6 N.C. 7 ADJ
8 OUT
Function
Input It is recommended to place a small ceramic capacitor (e.g. 100 nF), to GND, close to the IC terminals, in order to compensate line influences.
Not Connected
Enable Integrated pull-down resistor Enable the IC with high level input signal. Disable the IC with low level input signal.
Ground
Not Connected
Not Connected
Voltage Adjustment Connect an external voltage divider to determine the output voltage.
Output
Connect an output capacitor COUT to GND close to the IC’s terminals, respecting the
values specified for its capacitance and ESR in Table 2 “Functional Range” on Page 7.
Data Sheet
5 Rev. 1.0, 2015-02-04
4 General Product Characteristics
IFX30081SJV
General Product Characteristics
4.1 Absolute Maximum Ratings
Table 1 Absolute Maximum Ratings1)
Tj = -40°C to +125°C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Parameter
Symbol Min.
Values
Typ.
Max.
Unit
Note / Test Condition
Number
Voltage Input, Enable EN
Voltage
VIN, VEN -0.3
–
Voltage Output OUT, Voltage Adjustment ADJ
45 V –
P_4.1.1
Voltage Voltage Temperatures
VOUT -0.3 – VADJ -0.3 -
45 V – 7 V–
P_4.1.2 P_4.1.3
Junction Temperature Storage Temperature ESD Absorption
Tj Tstg
-40 – -55 –
150 °C 150 °C
– –
P_4.1.4 P_4.1.5
ESD Absorption
VESD,HBM -2
–
2
kV HBM2)
ESD Absorption
VESD,CDM -750
–
750 V
CDM3) at all pins
1) Not subject to production testing, specified by design.
2) ESD susceptibility, HBM Test according to ANSI/ESDA/JEDEC JS-001 (1.5kΩ, 100pF).
3) ESD susceptibility, Charged Device Model “CDM” according to JEDEC JESD22-C101
P_4.1.6 P_4.1.7
Note:
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed f.