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F25L01PA Dataheets PDF



Part Number F25L01PA
Manufacturers Elite Semiconductor
Logo Elite Semiconductor
Description 3V Only 1 Mbit Serial Flash Memory
Datasheet F25L01PA DatasheetF25L01PA Datasheet (PDF)

ESMT Flash „ FEATURES y Single supply voltage 2.7~3.6V y Standard, Dual SPI y Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 86MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 86MHz (100MHz / 172MHz equivalent Dual SPI) y Low power consumption - Active current: 22 mA - Standby current: 25 μ A - Deep Power Down current: 10 μ A y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Page programming time: 1.5 ms (typical) F25L01PA (2D) 3V.

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ESMT Flash „ FEATURES y Single supply voltage 2.7~3.6V y Standard, Dual SPI y Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz; 86MHz; 100MHz - Fast Read Dual max frequency: 50MHz / 86MHz (100MHz / 172MHz equivalent Dual SPI) y Low power consumption - Active current: 22 mA - Standby current: 25 μ A - Deep Power Down current: 10 μ A y Reliability - 100,000 typical program/erase cycles - 20 years Data Retention y Program - Page programming time: 1.5 ms (typical) F25L01PA (2D) 3V Only 1 M bit Serial Flash Memory with Dual Output y Erase - Chip erase time 1 sec (typical) - Block erase time 0.75 sec (typical) - Sector erase time 90 ms (typical) y Page Programming - 256 byte per programmable page y SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 y End of program or erase detection y Write Protect ( WP ) y Hold Pin ( HOLD ) y All Pb-free products are RoHS-Compliant „ ORDERING INFORMATION Product ID F25L01PA –50PG2D F25L01PA –86PG2D F25L01PA –100PG2D F25L01PA –50SG2D F25L01PA –86SG2D F25L01PA –100SG2D Speed 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz Package 8-lead SOIC 150 mil 8-pin TSSOP 173 mil (4.4mm) Comments Pb-free Pb-free „ GENERAL DESCRIPTION The F25L01PA is a 1Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 512 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device features sector erase architecture. The memory array is divided into 32 uniform sectors with 4K byte each; 2 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2013 Revision: 1.2 1/31 ESMT „ PIN CONFIGURATIONS 8- Lead SOIC (SOIC 8L, 150mil Body, 1.27mm Pin Pitch) CE 1 SO 2 WP 3 VSS 4 8 VDD 7 HOLD 6 SCK 5 SI F25L01PA (2D) 8- Pin TSSOP (TSSOP 8P, 173mil(4.4mm) Body, 0.65mm Pin Pitch) CE SO / SIO1 WP VSS 1 2 3 4 8 7 6 5 VDD HOLD SCK SI / SIO0 Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2013 Revision: 1.2 2/31 ESMT „ PIN DESCRIPTION Symbol SCK SI SO CE WP HOLD VDD VSS Pin Name Serial Clock Serial Data Input Serial Data Output Chip Enable Write Protect Hold Power Supply Ground Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. F25L01PA (2D) Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2013 Revision: 1.2 3/31 ESMT „ FUNCTIONAL BLOCK DIAGRAM F25L01PA (2D) Address Buffers and Latches X-Decoder Control Logic Flash Y-Decoder I/O Butters and Data Latches Serial Interface CE SCK SI SO WP HOLD „ SECTOR STRUCTURE Table 1: F25L01PA Sector Address Table Block 1 0 Sector 31 : 16 15 : 0 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB Address range 01F000H – 01FFFFH : 010000H – 010FFFH 00F000H – 00FFFFH : 000000H – 000FFFH Block Address A16 1 0 Elite Semiconductor Memory Technology Inc. Publication Date: Apr. 2013 Revision: 1.2 4/31 ESMT F25L01PA (2D) „ STATUS REGISTER The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register. Table 2: Software Status Register Bit Name Function 0 BUSY 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 WEL 1 = Device is memory Write enabled 0 = Device is not memory Write enabled 2 BP0 Indicate current level of block write protection (See Table 3) 3 BP1 Indicate current level of block write protection (See Table 3) 4 BP2 Indicate current level of block write protection (See Table 3) 5 TB Top / Bottom write protect 6 RESERVED Reserved for future use 7 BPL 1 = BP2,BP1,BP0 and TB are .


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