Document
FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13602-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90670/675 Series
MB90671/672/673/T673/P673 (MB90670 Series) MB90676/677/678/T678/P678 (MB90675 Series)
s DESCRIPTION
The MB90670/675 series is a member of 16-bit proprietary single-chip microcontroller F2MC*1-16L family designed to be combined with an ASIC (Application Specific IC) core. The MB90670/675 series is a high-performance general-purpose 16-bit microcontroller for high-speed real-time processing in various industrial equipment, OA equipment, and process control.
The instruction set of F2MC-16L CPU core inherits AT architecture of F2MC-8 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data (32-bit).
The MB90670/675 series has peripheral resources of UART0, UART1(SCI), an 8/10-bit A/D converter, an 8/16-bit PPG timer, a 16-bit reload timer, a 24-bit free run timer, an output compare (OCU), an input capture (ICU), DTP/external interrupt circuit, an I2C*2 interface (in MB90675 series only). Embedded peripheral resources performs data transmission with an intelligent I/O service function without the intervention of the CPU, enabling real-time control in various applications.
*1: F2MC stands for FUJITSU Flexible Microcontroller.
*2: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
s PACKAGES
80-pin Plastic LQFP
80-pin Plastic QFP
100-pin Plastic LQFP
100-pin Plastic QFP
(FPT-80P-M05)
(FPT-80P-M06)
(FPT-100P-M05)
(FPT-100P-M06)
MB90670/675 Series
s FEATURES
• Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at Vcc of 5.0 V)
• CPU addressing space of 16 Mbytes Internal addressing of 24-bit External accessing can be performed by selecting 8/16-bit bus width (external bus mode)
• Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) High code efficiency Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions
• Enhanced execution speed 4-byte instruction queue
• Enhanced interrupt function 8 levels, 32 factors
• Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS)
• Low-power consumpt.