ASM2P20805A

June 2005 ASM2P20805A rev 0.2 2.5V CMOS Dual 1-To-5 Clock Driver Features ƒ Advanced CMOS Technology ƒ Guaranteed low skew < 200pS (max.) ƒ Very low propagation delay < 2.5nS (max) ƒ Very low duty cycle distortion < 270pS (max) ƒ Very low CMOS power levels ƒ Operating frequency up to 166MHz ƒ TTL compatible inputs and outputs ƒ Two independent output banks with 3-state control ƒ 1:5 fanout per bank ƒ "Heartbeat" monitor output ƒ VCC = 2.5V ± 0.2V ƒ Available in SSOP and QSOP packages Functional Description The ASM2P20805A is a 2.5V Clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The ASM2P20805A offers low capacitance inputs. The ASM2P20805A is designed for high speed clock distribution where signal quality and skew are critical. The ASM2P20805A also allows single point-topoint transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram OEA INA INB OEB 5 OA1 – OA5 5 OB1 – OB5 MON Pin Diagram VCCA OA1 OA2 OA3 GNDA OA4 OA5 GNDQ OEA INA 1 20 2 A 19 3 S 18 4 M 2 17 5 P 16 2 6 0 15 7 8 14 0 8 5 13 9 A 12 10 11 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB Alli...