Document
UNISONIC TECHNOLOGIES CO., LTD
VGA7S019
Preliminary
7-CHANNEL INTEGRATED ESD SOLUTION FOR VGA PORT WITH INTEGRATED LEVEL SHIFTER AND MATCHING IMPEDANCE
TVS
DESCRIPTION
The UTC VGA7S019 is an ESD solution for the VGA or DVI-I port connector. This device integrates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the VIDEO, DDC and SYNC lines is implemented with low-capacitance current steering diodes.
Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage video controller ICs to provide design flexibility in multi-supply-voltage environments.
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC_SYNC, which is typically 5V. Additionally, each driver has a series termination resistor (RT) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. At the SYNC output the UTC VGA7S019 offers 65-Ω, 55-Ω, or 15-Ω series termination resistor option to match different transmission line impedances.
Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for the MOSFETs (VCC_DDC) should be connected to the supply rail (typically 3.3V) that supplies power to the transceivers of the DDC controller.
The UTC VGA7S019 confirms the IEC61000-4-2 (Level 4) system level ESD protection and ±15KV HBM ESD protection. This device is offered in space-saving SSOP-16 packages.
FEATURES
* 7 Channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level 4 ESD requirements (±8kV contact discharge) * Integrated impedance matching resistors on sync lines: –VGA7S019-15: 15Ω Termination –VGA7S019-55: 55Ω Termination –VGA7S019-65: 65Ω Termination
* Includes ESD protection, level-shifting, buffering and sync impedance matching
* 5V drivers for HSYNC and VSYNC lines * Very low loading capacitance from ESD protection diodes on VIDEO lines (2.5pF) * Bi-Directional level shifting N-Channel FETs provided for DDC_CLK and DDC_DATA channels * Flow-Through single-in-line pin mapping ensures no additional board layout burden while placing the ESD protection chip near the connector
www.unisonic.com.tw Copyright © 2014 Unisonic Technologies Co., Ltd
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QW-R223-024.b
VGA7S019
Preliminary
ORDERING INFORMATION
Note:
Ordering Number VGA7S019G-xx-R16-T VGA7S019G-xx-R16-R xx: Output Voltage, refer to Marking Information.
Package SSOP-16 SSOP-16
TVS
Packing Tube
Tape Reel
MARKING
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R223-024.b
VGA7S019
PIN CONFIGURATION
Preliminary
TVS
PIN DESCRIPTION
PIN NO.
1
2 3 4 5 6 7
8
9 10 11 12 13 14 15 16
PIN NAME
VCC_SYNC
VCC_VIDEO VIDEO1 VIDEO2 VIDEO3 GND
VCC_DDC
BYP
DDC_OUT1 DDC_IN1 DDC_IN2
DDC_OUT2 SYNC_IN1 SYNC_OUT1 SYNC_IN2 SYNC_OUT2
DESCRIPTION Isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associated ESD protection circuits Supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection circuits
High-speed ESD clamp input
Ground Isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates Bypass pin. Using a 0.2µF bypass capacitor will increase the ESD robustness of the system. DDC signal output. Connects to the video connector side of one of the sync lines.
DDC signal input. Connects to the VGA controller side of one of the sync lines.
DDC signal output. Connects to the video connector side of one of the sync lines. Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. Sync signal buffer output. Connects to the video connector side of one of the sync lines Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. Sync signal buffer output. Connects to the video connector side of one of the sync lines
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R223-024.b
VGA7S019
BLOCK DIAGRAM
Preliminary
VIDEO1
VIDEO2 VIDEO3 VCC_VIDEO
TVS
VCC_DDC DDC_IN1
DDC_IN2
GND RT
BYP VSYNC
SYNC_OUT1
RT DDC_OUT2 DDC_OUT1 SYNC_IN1 SYNC_IN2
SYNC_OUT2
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
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QW-R223-024.b
VGA7S019
Preliminary
TVS
ABSOLUTE MAXIMUM RATING over operating free-air temperature range (unless otherwise noted)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC_VIDEO, VCC_DDC, VCC_SYNC
-0.5~6.0
V
IO Voltage
VIDEOx Pins
VIO(VIDEO)
-0.5~VCC_VIDEO
V
Input Voltage
SYNC Pins
VI(SYNC)
-0.5~VCC_SYNC
V
Input Voltage
DDC_INx Pins
VI(DDC)
-0.5~6.0
V
Output Voltage
DDC_INx Pins
VO(DDC)
-0.5~6.0
V
IEC 61000-4-2 Contact VIDEO, DDC_OUT,
Discharge
SYNC_OUT Pins
±8 kV
H.