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U74LVC74A

Unisonic Technologies

DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS

UNISONIC TECHNOLOGIES CO., LTD U74LVC74A DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET  DESCRIPT...


Unisonic Technologies

U74LVC74A

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Description
UNISONIC TECHNOLOGIES CO., LTD U74LVC74A DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET  DESCRIPTION The U74LVC74A is a dual positive-edge-triggered D-type flip-flop. The preset ( PRE ) and clear ( CLR ) input can set or reset the output, egardless of the levels f others inputs. When the PRE and CLR are inactive(high),data at the data input meeting the set-up time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Following the hold-time interval, data D can be changed without affecting the levels at the outputs.  FEATURES * 1.65V to 3.6V VCC Operation * Inputs Accept Voltages to 5.5V * Max tpd at 5.2ns of 3.3V * Typical VOLP<0.8V at VCC=3.3V, TA=25°C * Typical VOHV>2V at VCC=3.3V, TA=25°C  ORDERING INFORMATION Ordering Number Lead Free Halogen Free U74LVC74AL-S14-R U74LVC74AG-S14-R U74LVC74AL-P14-R U74LVC74AG-P14-R Package SOP-14 TSSOP-14 CMOS IC Packing Tape Reel Tape Reel  MARKING www.unisonic.com.tw Copyright © 2014 Unisonic Technologies Co., Ltd 1 of 7 QW-R502-879.C U74LVC74A  PIN CONFIGURATION CMOS IC  FUNCTION TABLE (each gate) INPUT OUTPUT PRE CLR CLK D Q Q LHXXHL HLXXLH L L X X H H HH ↑ HHL HH ↑ L LH H H L X Q0 Q0 +: This configuration is unstable, as it is not persist when either PRE or CLR return to high level.  LOGIC DIAGRAM (positive logic) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 7 QW-R502-879.C U74LVC74A CMOS IC  ABSOLUTE MAXIMUM RATING (unless ...




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