P3P623S00B

P3P623S00B, P3P623S00E Product Preview Timing-Safet Peak EMI Reduction IC Functional Description P3P623S00B/E is a versatile, 3.3 V Zero−delay buffer designed to distribute Timing−Safe clocks with Peak EMI reduction. P3P623S00B is an eight−pin version, accepts one reference input and drives out one low−skew Timing−Safe clock. P3P623S00E accepts one reference input and drives out eight low−skew Timing−Safe clocks. P3P623S00B/E has an SS% that selects 2 different Deviation and associated Input−Output Skew (TSKEW). Refer to the Spread Spectrum Control and Input−Output Skew table for details. P3P623S00E has a CLKOUT for adjusting the Input−Output clock delay, depending upon the value of capacitor connected at this pin to GND. P3P623S00B/E operates from a 3.3 V supply and is available in two different packages, as shown in the ordering information table. Application P3P623S00B/E is targeted for use in Displays and memory interface systems. General Features Clock Distribution with Timing−Safe Peak EMI Reduction Input Frequency Range: 20 MHz − 50 MHz 2 Different Spread Selection Options Spread Spectrum can be Turned ON/OFF External Input−Output Delay Control Option Supply Voltage: 3.3 V ± 0.3 V P3P623S00B: 8 Pin SOIC P3P623S00E: 16 Pin TSSOP The First True Drop−in Solution These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com 8 1 SOIC−8 NB CASE 751 TSSOP−16 CASE 948AN PIN CONFIGURATION CLKIN 1 8 NC NC 2 SS% 3 P3P623S00B 7 ...