Document
Ordering number: ENA2069
LE24CBK23MC
CMOS IC
Dual port EEPROM Two Wire Serial Interface (2K+2K EEPROM)
http://onsemi.com
Overview
The dual port EEPROM series consists of two independent banks, and each bank can be controlled separately using dedicated control pins. The two banks can each be controlled separately, but share the internal power supply system. In addition, this product uses a 2-wire serial interface, and is the optimal device for realizing substantial reductions in system cost and mounting area, as well as low power consumption. This product also incorporates a combine mode that allows the two-bank configuration (2K bits + 2K bits) to be used as a pseudo-one-bank configuration (4K bits) by setting the COBM# pin to the low level. Together with the 16-byte page write function, this enables a reduction in the number of factory write processes. This product incorporates high performance CMOS EEPROM technology and realizes high-speed operation and high-level reliability. The interface of this product is compatible with the I2C bus protocol, making it ideal as a nonvolatile memory for small-scale parameter storage. In addition, this product also supports DDC2TM, so it can also be used as an EDID data storage memory for display equipment.
Functions
• Capacity
: 2K bits (256 × 8 bits) + 2K bits (256 × 8 bits): 4k bits in total
• Bank configuration
: 2-Bank (2k-bit + 2k-bit)
• Single supply voltage • Interface
: 2.5V to 5.5V : Two wire serial interface (I2C Bus*), VESA DDC2TM compliant**
• Operating clock frequency : 400kHz (max)
• Low power consumption : Standby: 5μA (max)
: One-bank read: 0.8 mA (max.)
• Automatic page write mode : 16 bytes
• Read mode • Erase/Write cycles
: Sequential read and random read : 106 cycles
• Data Retention
: 20 years
• Default data
: FFh(All address)
• High reliability
: Adopts proprietary symmetric memory array configuration
(USP6947325)
Noise filters connected to SCL1, SDA1, SCL2 and SDA2 pins
Incorporates a feature to prohibit write operations under low voltage conditions.
* : I2C Bus is a trademark of Philips Corporation. ** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013 July, 2013
62012 SY 20120111-S00002 No.A2069-1/21
Package Dimensions
unit:mm (typ) 3434
4.9 8
LE24CBK23MC
1 (0.55)
2 0.4
1.27
0.2
0.15 (1.5) 3.9 1.75 MAX 6.0 0.64
SANYO : SOP8J(200mil)
Pin Assignment
SCL2 1 SDA2 2
8 VDD 7 WP#
COBM# 3
6 SCL1
GND 4
5 SDA1
(Top view)
Pin Descriptions
PIN.1 PIN.2 PIN.3 PIN.4 PIN.5 PIN.6 PIN.7 PIN.8
SCL2 SDA2 COBM# GND SDA1 SCL1 WP# VDD
Clock input Data input/output
Bank2
Bank/Combine mode change
Ground
Data input/output Clock input
Bank1
Write protection
Power supply
No.A2069-2/21
Block Diagram
LE24CBK23MC
SCL1
SCL2
SDA1 SDA2 COBM# WP#
Input Buffer
I/O Buffer I/O Buffer Input Buffer Bank Controller & Mode Decoder
Input Buffer
Bank1
Write controller
High voltage generator
Condition detector Serial controller
Address generator X decoder
EEPROM Array (2K-bit)
Y decoder & Sense AMP Serial-Parallel converter
Bank2
Write controller
High voltage generator
Condition detector Serial controller
Address generator X decoder
EEPROM Array (2K-bit)
Y decoder & Sense AMP Serial-Parallel converter
Description of Operation
The Bank1 control signals are SCL1 and SDA1, and the Bank2 control signals are SCL2 and SDA2. The control signals for each bank can be controlled separately, regardless of the other bank’s status. This enables the product to be handled like two separate EEPROM mounted in a single package, which means that the Bank1 and Bank2 sides can be used simultaneously for two independent systems. Bank mode (2K bits + 2K bits) and combine mode (internally handled as 4K bits) can be switched using the COBM# pin. In combine mode, the Bank1 control signals (SCL1, SDA2) are used, and both Bank1 and Bank2 are accessed. This enables the two-bank configuration (2K bits + 2K bits) to be used as a pseudo-one-bank configuration (4K bits), which allows access to both the Bank1 and Bank2 areas using a single system of control signals (SCL1, SDA1). Data correlation is guaranteed between combine mode and bank mode, enabling operation while switching the mode, such as performing write in combine mode and read in bank mode.
No.A2069-3/21
LE24CBK23MC
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Supply voltage
DC input voltage
Over-shoot voltage
Below 20ns
Storage temperature
Tstg
Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Ratings -0.5 to +6.5 -0.5 to +5.5 -1.0 to +6.5 -65 to +150
Unit V V V °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure t.