IDT82V3396

Dual Synchronous Ethernet Line Card PLL Short Form Datasheet IDT82V3396 FEATURES HIGHLIGHTS Dual PLL chip: Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE) Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-4) jitter generation requirements Provides node clocks for Cellular and WLL base-station (GSM and 3G networks) Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applications MAIN FEATURES Employs PLL architecture to feature excellent jitter performance and minimize the number of external components Integrates 2 DPLLs; one can be used on the transmit path and the other on the receive path Supports programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and 560 Hz Provides OUT1~OUT6 output clock frequencies up to 644.53125 MHz Includes 25MHz, 125 MHz and 156.25 MHz for CMOS outputs Includes 25.78125MHz, 128.90625 MHz and 161.1328125 MHz for CMOS outputs Includes 25MHz, 125 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential outputs Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, 322.265625 MHz and 644.53125 MHz for differential outputs Provides IN1~IN6 input clock frequencies cover from 2 kHz to 156.25 MHz Supports Forced or Automatic operating mode switch controlled by an internal state machine. It supports Free- Run, Locked and Holdover modes Supports manual and automatic selected input clock switch Supports automatic hitless selected input clock switch on clock fail- ure Supports three types of input clo...