3.3V / 5.0V Ultra-Low Skew 1:4 Clock Fanout Buffer
SB3N551
3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
Description The SB3N551 is a low skew 1−to−4 clock fanout ...
Description
SB3N551
3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer
Description The SB3N551 is a low skew 1−to−4 clock fanout buffer, designed
for clock distribution in mind. The SB3N551 specifically guarantees low output−to−output skew. Optimal design, layout and processing minimize skew within a device and from device to device.
The output enable (OE) pin three−states the outputs when low.
Features
Input/Output Clock Frequency up to 160 MHz Low Skew Outputs (50 ps typical) RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical) Output goes to Three−State Mode via OE Operating Range: VDD = 3.0 V to 5.5 V Ideal for Networking Clocks Packaged in 8−pin SOIC Industrial Temperature Range These are Pb−Free Devices
Q1
Q2 CLK
Q3
Q4
OE Figure 1. Block Diagram
http://onsemi.com
8 1
SOIC−8 D SUFFIX CASE 751
MARKING DIAGRAMS* 8
3N551 ALYW
G 1
3N551 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package
PIN CONNECTIONS
1 ICLK
2 Q1
3 Q2
4 Q3
8 OE
7 VDD
6 GND
5 Q4
ORDERING INFORMATION
Device SB3N551DG
SB3N551DR2G
Package
Shipping†
SOIC−8 (Pb−Free)
98 Units/Rail
SOIC−8 2500/Tape & Reel (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
January, 2015 − Rev. 0
1
Publication Order Number: SB3N551/D
SB3N551
Table 1. OE, OUTPUT ENABLE FUNCTION ...
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