Double DATA RATE SDRAM
Revision History
Revision 0.1 (Jan. 2013) -First release.
Revision 0.2 (Feb. 2014) - Update DC current.
Revision 0.3 (Ap...
Description
Revision History
Revision 0.1 (Jan. 2013) -First release.
Revision 0.2 (Feb. 2014) - Update DC current.
Revision 0.3 (Apr. 2014) - Update Temperature.
EM44CM1688LBC
Apr. 2014
1/29
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EM44CM1688LBC
1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM
Features
JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
All inputs and outputs are compatible with SSTL_18
interface. Fully differential clock inputs (CK, /CK) operation. Eight Banks Posted CAS Bust length: 4 and 8. Programmable CAS Latency (CL): 5, 6 Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5 Write Latency (WL) =Read Latency (RL) -1. Read Latency (RL) = Programmable Additive
Latency (AL) + CAS Latency (CL) Bi-directional Differential Data Strobe (DQS). Data inputs on DQS centers when write. Data outputs on DQS, /DQS edges when read. On chip DLL align DQ, DQS and /DQS transition
with CK transition. DM mask write data-in at the both rising and falling
edges of the data strobe. Sequential & Interleaved Burst type available. Off-Chip Driver (OCD) Impedance Adjustment On Die Termination (ODT) Auto Refresh and Self Refresh 8,192 Refresh Cycles / 64ms Average Refresh Period 7.8us at lower than Tcase 85
°C, 3.9us at 85°C < Tcase ≦ 95°C RoHS Compliance Partial Array Self-Refresh (PASR) High Temperature Self-Refresh rate enable
Description
The EM44CM1688LBC is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,7...
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