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ON Semiconductort
JFET Input Operational Amplifiers
These low cost JFET input operational amplifiers combine two state–of–the–art analog technologies on a single monolithic integrated circuit. Each internally compensated operational amplifier has well matched high voltage JFET input devices for low input offset voltage. The JFET technology provides wide bandwidths and fast slew rates with low input bias currents, input offset currents, and supply currents.
These devices are available in single, dual and quad operational amplifiers which are pin–compatible with the industry standard MC1741, MC1458, and the MC3403/LM324 bipolar devices.
• Input Offset Voltage of 5.0 mV Max (LF347B) • Low Input Bias Current: 50 pA • Low Input Noise Voltage: 16 nV/ǸHz • Wide Gain Bandwidth: 4.0 MHz • High Slew Rate: 13V/µs • Low Supply Current: 1.8 mA per Amplifier • High Input Impedance: 1012 Ω • High Common Mode and Supply Voltage Rejection Ratios: 100 dB
MAXIMUM RATINGS Rating
Supply Voltage
Differential Input Voltage Input Voltage Range (Note 1) Output Short Circuit Duration (Note 2) Power Dissipation at TA = +25°C
Derate above TA =+25°C Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range
Symbol
VCC VEE VID VIDR tSC PD 1/θJA TA TJ Tstg
Value
Unit
+18 V –18
±30 V
±15 V
Continuous
900 mW 10 mW/°C
0 to +70
°C
115 °C
– 65 to +150
°C
NOTES: 1. Unless otherwise specified, the absolute maximum negative input voltage is limited to the negative power supply.
2. Any amplifier output can be shorted to ground indefinitely. However, if more than one amplifier output is shorted simultaneously, maximum junction temperature rating may be exceeded.
LF347, B LF351 LF353
FAMILY OF JFET OPERATIONAL AMPLIFIERS
8 1
8 1
N SUFFIX PLASTIC PACKAGE
CASE 626
D SUFFIX PLASTIC PACKAGE
CASE 751 (SO–8)
PIN CONNECTIONS
Offset Null 1 Invt Input 2 Noninvt Input 3
VEE 4
+
8 NC 7 VCC 6 Output 5 Offset Null
LF351 (Top View)
Output A 1
8 VCC
2 - 7 Output B
Inputs A
3 +A
-6
Inputs B
VEE 4
B+ 5
LF353 (Top View)
N SUFFIX PLASTIC PACKAGE
CASE 646
14
1
PIN CONNECTIONS
Out 1 1
Inputs 1
2 3
VCC 4
Inputs 2
5 6
+ + -
Out 2 7
1 2
14 Out 4
- 13
Inputs 4
4
12
+
11 VEE
+
10
3 -9
Inputs 3
8 Out 3
(Top View)
Device
ORDERING INFORMATION
Operating Function Temperature Range
Package
LF351D LF351N
Single Single
SO–8 Plastic DIP
LF353D LF353N
Dual Dual
TA = 0° to +70°C
SO–8 Plastic DIP
LF347BN Quad LF347N Quad
Plastic DIP Plastic DIP
© Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 1
1
Publication Order Number: LF347/D
LF347, B LF351 LF353
ELECTRICAL CHARACTERISTICS (VCC = +15 VEE = –15 V, TA = 25°C, unless otherwise noted.)
LF347B
LF347, LF351, LF353
Characteristic
Symbol
Min
Typ
Max
Min
Typ Max
Unit
Input Offset Voltage (RS ≤ 10 k, VCM = 0) TA = +25°C 0°C ≤ TA ≤ +70°C
VIO mV – 1.0 5.0 – 5.0 10
– – 8.0 – – 13
Avg. Temperature Coefficient of Input Offset Voltage ∆VIO/∆T
RS ≤ 10 k, 0°C ≤ TA ≤ +70°C
– 10 –
µV/°C – 10 –
Input Offset Current (VCM = 0, Note 3) TA = +25°C 0°C ≤ TA ≤ +70°C
IIO
–
25 100
–
25 100
pA
– – 4.0 – – 4.0 nA
Input Bias Current (VCM = 0, Note 3) TA = +25°C 0°C ≤ TA ≤ +70°C
IIB
–
50 200
–
50 200
pA
– – 8.0 – – 8.0 nA
Input Resistance
ri
– 1012 –
– 1012 –
Ω
Common Mode Input Voltage Range
VICR ±11 +15 – ±11 +15 – –12 –12
V
Large–Signal Voltage Gain (VO = ±10 V, RL = 2.0 k) TA = +25°C 0°C ≤ TA ≤ +70°C
AVOL
50 100 25 –
– –
V/mV
25 100
–
15 –
–
Output Voltage Swing (RL = 10 k)
VO ±12 ±14 – ±12 ±14 –
V
Common Mode Rejection (RS ≤ 10 k)
CMR
80 100
–
70 100
–
dB
Supply Voltage Rejection (RS ≤ 10 k)
PSRR
80 100
–
70 100
–
dB
Supply Current LF347 LF351 LF353
ID mA – 7.2 11 – 7.2 11 – – – – 1.8 3.4 – – – – 3.6 6.5
Short Circuit Current Slew Rate (AV = +1) Gain–Bandwidth Product
ISC SR BWp
– 25 – – 13 – – 4.0 –
– 25 – mA – 13 – V/µs – 4.0 – MHz
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1000 Hz)
Equivalent Input Noise Current (f = 1000 Hz)
en
– 24 –
– 24 – nV/√ Hz
in
– 0.01 –
– 0.01 – pA/ √ Hz
Channel Separation (LF347, LF353) 1.0 Hz ≤ f ≤ 20 kHz (Input Referred)
–
– –120 –
– –120 –
dB
For Typical Characteristic Performance Curves, refer to MC34001, 34002, 34004 data sheet.
NOTE: 3. Input bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature. To maintain junction temperatures as close to ambient as is possible, pulse techniques are utilized during test.
http://onsemi.com 2
LF347, B LF351 LF353
OUTLINE DIMENSIONS
NOTE 2
85
14
F –A–
–B–
N SUFFIX PLASTIC PACKAGE
CASE 626–05 ISSUE K
L
–T–
SEATING PLANE
H
C
J
N
DK
M
G
0.13 (0.005) M T A M B M
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240.