MC100EP196A

MC100EP196A 3.3 V ECL Programmable Delay Chip With FTUNE The MC100EP196A is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It has similar architecture to the EP195 with the added feature of further tunability in delay using the FTUNE pin. The FTUNE input takes an http://onsemi.com analog voltage from VCC to VEE to fine tune the output delay from 0 to 60 ps. MARKING The delay section consists of a programmable matrix of gates and DIAGRAM* multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP196A has a digitally selectable resolution of about 1 10 ps and a net range of up to 10.4 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent 1 32 QFN32 MN SUFFIX CASE 488AM MC100 EP196A ALYWG changes in D[10:0]. The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in A = Assembly Location Table 6 and Figure 3. The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level signals. Because the MC100EP196A is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin L = Wafer Lot Y = Year W = W...