Document
74HC139-Q100; 74HCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
Rev. 1 — 19 June 2014
Product data sheet
1. General description
The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C
Input levels: For 74HC139-Q100: CMOS level For 74HCT139-Q100: TTL level
Demultiplexing capability 2 independent 2-to-4 decoders Multifunction capability Suitable for memory decoding, data routing or code conversion Complies with JEDEC standard no. 7A Active LOW mutually exclusive outputs ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options
NXP Semiconductors
74HC139-Q100; 74HCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC139D-Q100
40 C to +125 C SO16
74 HCT139D-Q100
74HC139DB-Q100 40 C to +125 C SSOP16
74HCT139DB-Q100
74HC139PW-Q100 40 C to +125 C TSSOP16
74HCT139PW-Q100
Description plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 5.3 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
Version SOT109-1
SOT338-1
SOT403-1
4. Functional diagram
( <
$ < <
$ < <
$ < <
$ <
( DDD
Fig 1. Logic symbol
$ $
(
$ $
(
'(&2'(5 '(&2'(5
< < < <
< < < <
Fig 2. Functional diagram
DDD
74HC_HCT139_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 18
NXP Semiconductors
74HC139-Q100; 74HCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
';
*
';
*
DDD
a.
Fig 3. IEC Logic symbol
$ $
(
Fig 4. Logic diagram (one decoder/demultiplexer)
;<
(1
;<
(1
DDD
b.
< < < <
DDD
74HC_HCT139_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 18
NXP Semiconductors
74HC139-Q100; 74HCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
5. Pinning information
5.1 Pinning
+&4 +&74
( $ $ < < < < *1'
Fig 5. Pin configuration SO16, SSOP16 and TSSOP16
9&& ( $ $ < < < <
DDD
5.2 Pin description
Table 2. Pin description Symbol 1E, 2E 1A0, 1A1 1Y0, 1Y1, 1Y2, 1Y3 GND 2Y0, 2Y1, 2Y2, 2Y3 2A0, 2A1 VCC
Pin 1, 15 2, 3 4, 5, 6, 7 8 12, 11, 10, 9 14, 13 16
6. Functional description
Description enable input (active LOW) address input output (active LOW) ground (0 V) output (active LOW) address input positive supply voltage
Table 3. Control nE H L L L L
Function table[1] Input nA1 X L L H H
nA0 X L H L H
Output nY3 H H H H L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
nY2 H H H L H
nY1 H H L H H
nY0 H L H H H
74HC_HCT139_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 18
NXP Semiconductors
74HC139-Q100; 74HCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage IIK input clamping current IOK output clamping current IO output current
VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V VO = 0.5 V to (VCC + 0.5 V)
0.5 +7 - 20 - 20 - 25
V mA mA mA
ICC IGND Tstg Ptot
supply current ground current storage temperature total power dissipation
SO16 package
- 50 mA
50 -
mA
65 +150 C
[1] -
500 mW
SSOP16 package
[2] -
500 mW
TSSOP16 package
[2] -
500 mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. [2] For SSOP16 and TSSOP16 packages: Ptot derates linearly.