CH7512B

Chrontel CH7512B Brief Datasheet CH7512B DP to LVDS Monitor Controller FEATURES Supports DisplayPort Specification version 1.1a Support 2 Main Link Lanes at either 1.62Gb/s or 2.7Gb/s link rate for notebook PC applications Supports input color depth 6, 8-bit per pixel in RGB format Supports Enhanced Framing Mode Support VESA and CEA timing standards up to 1920x1200 resolution in 8-bit input with 60Hz refresh rate HDCP engine compliant with HDCP 1.3 specification with internal HDCP Keys Support dynamic refresh rate switching Support Gamma correction Panel tuning methods including dithering and 6-bit + FRC Fast and full Link Training for DisplayPort system 2 work modes: connect 27MHz crystal, inject 27MHz clock Programmable LCD panel power sequence Support 18-bit Single Port, 18-bit Dual Port, 24-bit Single Port and 24-bit Dual Port LVDS output interface Support both OpenLDI and SPWG bit mapping for LVDS application Support panel select by GPIO pins control or writing the chip registers. Flexible LVDS output pins swapping Blank panel during invalid input Supports PWM. Backlight luminance level control through AUX channel, PWM pin and BLUP/BLDN pin Support Dynamic Backlight Control Support OSD display when BLUP/BLDN pins control Backlight Luminance Hot Plug Detection Loads Boot ROM automatically upon power up Serial BOOT ROM data updated through I2C bus or AUX Channel Programmable power management EMI reduction capability for DP ...