Document
Rev. 1.0, May. 2012 KMS5U000KM-B308
MCP Specification
4GB e·MMC + 4Gb DDP(64M x32+ 64Mx32) Mobile DDR SDRAM
datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2012 Samsung Electronics Co., Ltd. All rights reserved.
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KMS5U000KM-B308
datasheet
Revision History
Revision No. 0.0
1.0
History
Initial issue. - 4GB e·MMC B-die_ Ver 0.0 - 4Gb DDP Mobile DDR SDRAM D-die_Ver 1.0
- Final datasheet.
Draft Date May. 09 , 2012
May. 15 , 2012
Rev. 1.0
MCP Memory
Remark Preliminary
Editor K.N.Kang
Fianl
K.N.Kang
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KMS5U000KM-B308
datasheet
Rev. 1.0
MCP Memory
1. FEATURES
Operating Temperature : -25C ~ 85C Package : 153ball FBGA Type - 11.5 x 13 x 1.0mmt, 0.5mm pitch
MultiMediaCard System Specification Ver. 4.41 compatible. Detail description is referenced by JEDEC Standard SAMSUNG e·MMC supports below special features which are being discussed in JEDEC - High Priority Interrupt scheme is supported - Back ground operation is supported. Full backward compatibility with previous MultiMediaCard system ( 1bit data bus, multi-e·MMC systems) Data bus sidth :1bit(Default), 4bit and 8bit MMC I/F Clock Frequency : 0 ~ 52MHz
MMC I/F Boot Frequency : 0 ~ 52MHz Dual Data Rate mode is supported Power : Interface power → VDD = VCCQm(1.70V ~ 1.95V or 2.7V ~ 3.6V) , Memory power → VDDF = VCCm(2.7V ~ 3.6V)
• VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle. • Bidirectional data strobe (DQS). • Four banks operation. • Differential clock inputs (CK and CK). • MRS cycle with address key programs. - CAS Latency (3) - Burst Length (2, 4, 8, 16) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs. - Partial Array Self Refresh (Full, 1/2, 1/4 Array) - Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8) • Internal Temperature Compensated Self Refresh. • All inputs except data & DM are sampled at the positive going edge of the
system clock (CK). • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • DM for write masking only. • Auto refresh duty cycle. • 7.8us •Clock Stop capability.
Operating Frequency
Speed @CL31)
DDR400 200MHz
NOTE : 1) CAS Latency
ADDRESS CONFIGURATION
Organization
64M x32 64M x32
CS
CKE
Bank Address
Row Address
CS0 CKE0 BA0, BA1 A0 - A13
CS1 CKE1 BA0, BA1 A0 - A13
Column Address
A0 - A9
A0 - A9
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KMS5U000KM-B308
datasheet
Rev. 1.0
MCP Memory
2. GENERAL DESCRIPTION
The KMS5U000KM is a Multi Chip Package Memory which combines 4GB e·MMC and 4Gb DDP Mobile DDR synchronous high data rate Dynamic RAM.
The SAMSUNG e·MMC is an embedded MMC solution designed in a BGA package form. e·MMC operation is identical to a MMC card and therefore is a simple read and write to memory using MMC protocol v4.5 which is a industry standard. e·MMC consists of NAND flash and a MMC controller. 3V supply voltage is required for the NAND area (VDDF) whereas 1.8V or 3V dual supply voltage (VDD) is supported for the MMC controller. Maximum MMC interface frequency of 52MHz and maximum bus widths of 8 bit are supported. There are several advantages of using e·MMC. It is easy to use as the MMC interface allows easy integration with any microprocessor with MMC host. Any revision or amendment of NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host. This leads to faster product development as well as faster times to market. The embedded flash mangement software or FTL(Flash Transition Layer) of e·MMC manages Wear Leveling, Bad Block Management and ECC. The FTL supports all features of the Samsung NAND flash and achieves optimal performance.
In 4Gb DDP Mobile DDR SDRAM, Synchronous design make a device controlled precisely with the use of system clock. Range of operating freq.