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74VHC299 Dataheets PDF



Part Number 74VHC299
Manufacturers National Semiconductor
Logo National Semiconductor
Description 8-Input Universal Shift/Storage Register
Datasheet 74VHC299 Datasheet74VHC299 Datasheet (PDF)

74VHC299 8-Input Universal Shift Storage Register with Common Parallel I O Pins PRELIMINARY November 1995 74VHC299 8-Input Universal Shift Storage Register with Common Parallel I O Pins General Description The VHC299 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation The VHC299 is an 8-bit universal shift storage register with TRI-STA.

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74VHC299 8-Input Universal Shift Storage Register with Common Parallel I O Pins PRELIMINARY November 1995 74VHC299 8-Input Universal Shift Storage Register with Common Parallel I O Pins General Description The VHC299 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation The VHC299 is an 8-bit universal shift storage register with TRI-STATE outputs Four modes of operation are possible hold (store) shift left shift right and load data The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins Additional outputs are provided for flip-flops Q0 Q7 to allow easy serial cascading A separate active LOW Master Reset is used to reset the register An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage This device can be used to interface 5V to 3V systems and two supply systems such as battery backup This circuit prevents device destruction due to mismatched supply and input voltages Features Y Low power dissipation ICC e 4 mA at TA e 25 C Y High noise immunity VNIH e VNIL e 28% VCC (min) Y All inputs are equipped with a power down protection function Y Balanced propagation delays tPLH j tPHL Y Low noise VOLP e 0 9V (typ) Y Pin and function compatible with 74HC299 Commercial 74VHC299M 74VHC299SJ 74VHC299MTC 74VHC299N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Molded JEDEC SOIC 20-Lead Molded EIAJ SOIC 20-Lead Molded JEDEC Type 1 TSSOP 20-Lead Molded DIP Note Surface mount packages are also available on Tape and Reel Specify by appending the suffix letter ‘X’ to the ordering code Logic Symbols Connection Diagram IEEE IEC Pin Assignment for DIP TSSOP and SOIC TL F 11638–1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11638 TL F 11638 – 3 TL F 11638 – 2 RRD-B30M125 Printed in U S A Pin Names CP DS0 DS7 S0 S1 MR OE1 OE2 I O0 – I O7 Q0 Q7 Description Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset TRI-STATE Output Enable Inputs Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs Functional Description The VHC299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left shift right parallel load and hold operations The type of operation is determined by S0 and S1 as shown in the Truth Table All flip-flop outputs are brought out through TRI-STATE buffers to separate I O pins that also serve as data inputs in the parallel load mode Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops All other state changes are initiated by the rising edge of the clock Inputs can change when the clock is in either state provided only that the recommended setup and hold times relative to the rising edge of CP are observed A HIGH signal on either OE1 or OE2 disables the TRISTATE buffers and puts the I O pins in the high impedance state In this condition the shift hold load and reset operations can still occur The TRI-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation Truth Table Inputs MR S1 S0 L XX CP X H H HL H L HL H H LL H LL X H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Transition Response Asynchronous Reset Q0 – Q7 e LOW xParallel Load I On Qn xShift Right DS0 Q0 xQ0 Q1 etc xShift Left DS7 Q7 xQ7 Q6 etc Hold 2 Logic Diagram TL F 11638 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering 10 seconds) b0 5V to a7 0V b0 5V to a7 0V b0 5V to VCC a 0 5V b20 mA g20 mA g25 mA g75 mA b65 C to a150 C 260 C Note 1 Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation outside databook specifications Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr tf) VCC e 3 3V g0 3V VCC e 5 0V g0 5V 2 0V to a5 5V 0V to a5 5V 0V to VCC b40 C to a85 C 0 E 100 ns V 0 E 20 ns V DC Charac.


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