Document
STB42N60M2-EP, STP42N60M2-EP, STW42N60M2-EP
N-channel 600 V, 0.076 Ω typ., 34 A MDmesh™ M2 EP Power MOSFETs in D²PAK, TO-220 and TO-247 packages
Datasheet - production data
TAB
D²PAK
2 3
1
TAB
TAB
TO-220
1 23
TO-247
23 1
Features
Order code
VDS @ TJmax RDS(on) max. ID
STB42N60M2-EP
STP42N60M2-EP
650 V
0.087 Ω 34 A
STW42N60M2-EP
• Extremely low gate charge • Excellent output capacitance (COSS) profile • Very low turn-off switching losses • 100% avalanche tested • Zener-protected
Figure 1: Internal schematic diagram
D(2, TAB)
Applications
• Switching applications • Tailored for very high frequency converters
(f > 150 kHz)
G(1)
S(3)
Order code STB42N60M2-EP STP42N60M2-EP STW42N60M2-EP
Description
These devices are N-channel Power MOSFETs developed using MDmesh™ M2 EP enhanced performance technology. Thanks to their strip layout and improved vertical structure, the devices exhibit low on-resistance and optimized switching characteristics with very low turn-off switching losses, rendering them suitable for the most demanding very high frequency converters.
AM01476v1
Table 1: Device summary
Marking
Package
Packaging
42N60M2EP
D²PAK TO-220 TO-247
Tape and reel Tube
January 2015
DocID027327 Rev 1
This is information on a product in full production.
1/20
www.st.com
Contents
Contents
STB42N60M2-EP, STP42N60M2-EP, STW42N60M2-EP
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.2 Electrical characteristics (curves)...................................................... 6
3 Test circuits ..................................................................................... 9
4 Package mechanical data ............................................................. 10
4.1 D²PAK package information ............................................................ 10 4.2 TO-220 type A package information................................................ 13 4.3 TO-247 package information........................................................... 15
5 Packaging mechanical data.......................................................... 17
6 Revision history ............................................................................ 19
2/20 DocID027327 Rev 1
STB42N60M2-EP, STP42N60M2-EP, STW42N60M2-EP
Electrical ratings
1 Electrical ratings
Symbol
Table 2: Absolute maximum ratings
Parameter
Value
VGS ID ID IDM(1) PTOT dv/dt(2) dv/dt(3)
Tstg Tj
Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Peak diode recovery voltage slope MOSFET dv/dt ruggedness Storage temperature Max. operating junction temperature
± 25 34 22 136 250 15 50 - 55 to 150 150
Notes: (1)Pulse width limited by safe operating area. (2)ISD ≤ 34 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V. (3)VDS ≤ 480 V
Unit V A A A W
V/ns V/ns °C °C
Symbol
Table 3: Thermal data
Parameter
D²PAK
Value TO-220
Rthj-case Rthj-pcb(1)
Thermal resistance junction-case max Thermal resistance junction-pcb max
0.50 30
Rthj-amb
Thermal resistance junction-ambient max
62.5
Notes: (1)When mounted on FR-4 board of inch², 2oz Cu.
TO247
50
Unit
°C/W °C/W °C/W
Symbol IAR EAS
Table 4: Avalanche characteristics Parameter
Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax)
Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V)
Value 6
800
Unit A mJ
DocID027327 Rev 1
3/20
Electrical characteristics
STB42N60M2-EP, STP42N60M2-EP, STW42N60M2-EP
2 Electrical characteristics
TC = 25 °C unless otherwise specified
Table 5: On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown voltage
VGS = 0 V, ID = 1 mA
IDSS
Zero gate voltage Drain current
IGSS VGS(th)
RDS(on)
Gate-body leakage current
Gate threshold voltage Static drain-source onresistance
VGS = 0 V, VDS = 600 V VGS = 0 V, VDS = 600 V, TC = 125 °C VDS = 0 V, VGS = ±25 V VDS = VGS, ID = 250 µA
VGS = 10 V, ID = 17 A
Min. Typ. Max. Unit
600 V
1 µA
100 µA
±10 µA
23
4V
0.076 0.087 Ω
Symbol
Parameter
Ciss Input capacitance
Coss Output capacitance
Crss
Reverse transfer capacitance
Coss
(1) eq.
Equivalent output capacitance
RG Intrinsic gate resistance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge
Table 6: Dynamic Test conditions
VDS= 100 V, f = 1 MHz, VGS = 0 V
Min. -
Typ. Max. Unit 2370 - pF 112 - pF
- 2.5 - pF
VDS = 0 to 480 V, VGS = 0 V
f = 1 MHz, ID = 0 A
VDD = 480 V, ID = 34 A, VGS = 10 V (see Figure 18: "Gate charge test circuit")
-
-
454 - pF
4.5 - Ω 55 - nC 8.5 - nC 25 - nC
Notes: (1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
Symbol
Parameter
Table 7: Switching energy Test conditions
E(off)
Turn-off ener.