K4S560432E-NCL75

SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 256Mb E-die SDRAM Specification 54pin sTSOP-II Revision 1.0 August. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) Revision History Revision 1.0 (August. 2003) - First release. CMOS SDRAM Rev. 1.0 August, 2003 SDRAM 256Mb E-die (x4, x8, x16) CMOS SDRAM 16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (8K Cycle) GENERAL DESCRIPTION The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performanc...