Document
A3S56D30GTP A3S56D40GTP
256M Double Data Rate Synchronous DRAM
256Mb DDR SDRAM Specification
A3S56D30GTP A3S56D40GTP
Zentel Electronics Corp.
Revision 1.1
Jul., 2013
A3S56D30GTP A3S56D40GTP
256M Double Data Rate Synchronous DRAM
General Description
A3S56D30GTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40GTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40GTP achieves very high speed clock rate up to 200 MHz .
Features
- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - CAS latency - 2 / 2.5 / 3 (programmable)
Burst length - 2 / 4 / 8 (programmable) Burst type - Sequential / Interleave (programmable) - Auto Precharge / All Bank Precharge controlled by A10 - Support concurrent Auto Precharge - 8192 refresh cycles / 64ms (4 banks concurrent refresh) - Auto Refresh and Self Refresh - Row address A0-12 / Column address A0-9(x8) /A0-8(x16) - SSTL_2 Interface - Package 400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch
Zentel Electronics Corporation reserve the right to change products or specification without notice.
Revision 1.1
Page 1 / 40
Jul., 2013
A3S56D30GTP A3S56D40GTP
256M Double Data Rate Synchronous DRAM
Pin Assignment (Top View) 66-pin TSOP
x8 x16
VDD
DQ0 VDDQ
NC
DQ1 VSSQ
NC
DQ2 VDDQ
NC
DQ3 VSSQ
NC
NC VDDQ
NC NC VDD NC
NC /WE /CAS /RAS /CS NC BA0
BA1 A10/AP
A0
A1 A2 A3
VDD
VDD DQ0 VDDQ DQ1
DQ2 VSSQ
DQ3
DQ4 VDDQ
DQ5
DQ6 VSSQ
DQ7
NC VDDQ LDQS
NC VDD
NC
LDM /WE /CAS /RAS /CS NC BA0
BA1 A10/AP
A0
A1 A2 A3
VDD
1
2 3 4
5 6 7
8 9 10
11 12 13
14 15 16
17 18 19
20 21 22 23
24 25 26
27 28 29
30 31 32
33
66pin TSOP(II)
400mil width x
875mil length
0.65mm Lead Pitch
Row A0-12
Column A0-9 (x8) A0-8 (x16)
66
65 64 63
62 61 60
59 58 57
56 55 54
53 52 51
50 49 48
47 46 45 44
43 42 41
40 39 38
37 36 35
34
CLK, /CLK CKE /CS /RAS /CAS /WE
DQ0-15 DQ0-7 UDM, LDM DM UDQS, LDQS DQS
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable
: Data I/O (x16) : Data I/O (x8) : Write Mask (x16) : Write Mask (x8) : Data Strobe (x16) : Data Strobe (x8)
A0-12 BA0,1 VDD VDDQ VSS VSSQ
VREF
VSS
DQ15 VSSQ DQ14
DQ13 VDDQ DQ12
DQ11 VSSQ DQ10
DQ9 VDDQ DQ8 NC VSSQ UDQS
NC VREF VSS UDM /CLK CLK CKE NC A12 A11
A9 A8 A7 A6 A5 A4
VSS
VSS
DQ7 VSSQ NC
DQ6 VDDQ NC
DQ5 VSSQ NC
DQ4 VDDQ NC NC VSSQ DQS
NC VREF VSS DM /CLK CLK CKE NC A12 A11
A9 A8 A7 A6 A5 A4
VSS
: Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output
: SSTL_2 reference voltage
Revision 1.1
Page 2 / 40
Jul., 2013
A3S56D30GTP A3S56D40GTP
256M Double Data Rate Synchronous DRAM
Pin Function
SYMBOL CLK, /CLK
CKE /CS /RAS, /CAS, /WE A0-12 BA0,1
TYPE Input
Input Input Input Input Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls Power Down and Self Refresh. Taking CKE LOW provides Precharge Power Down or Self Refresh (all banks idle), or Active Power Down (row active in any bank). Taking CKE HIGH provides Power Down exit or Self Refresh exit. After Self Refresh is started, CKE becomes asynchronous input. Power Down and Self Refresh is maintained as long as CKE is LOW.
Chip Select: When /CS is HIGH, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is HIGH at a Read / Write command, an Auto Precharge is performed. When A10 is HIGH at a Precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with Active, Precharge, Read, Write commands.
DQ0-7 (x8),
Input / Output Data Input/Output: Data bus
DQ0-15 (x16),
DQS (x8)
Input / Output
UDQS, LDQS (x16)
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15
DM (x8) UDM, LDM (x16)
Input
Input Data.