A3S28D40FTP Datasheet

A3S28D40FTP 128M Double Data Rate Synchronous DRAM

A3S28D30FTP is a 4-bank x 4,194,304-word x 8bit, A3S28D40FTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output dat.

Features

- Vdd=VddQ=2.5V+0.2V (-4, -5E, -5) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - /CAS latency - 2.0 / 2.5 / 3.0 / 4.0 (programmable) ; Burst length - 2 / 4 / 8 (programmable) Burst type - Sequential / Interleave (programmable) - Auto .