Document
:010-8287 3941/42/43/44 :010-8287 3945 http://www.echip.com.cn
256Mb Synchronous DRAM Specification
Z2V56S20BTP Z2V56S30BTP Z2V56S40BTP
Deutron Electronics Corp.
8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C.
TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw
256Mb Synchronous DRAM :010-8287 3941/42/43/44 :010-8287 3945 http://www.echip.com.cn
256Mb Synchronous DRAMP2V56S20BTP(4-BANKx16,777,216-WORDx4-BIT) P2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) P2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
ORDERING INFORMATION
Frequency Speed(ns)
Type
Order Part Number Low Power Package
Standard Low Power Pb-Free and Pb-Free
166MHz
6
Z2V56S20/30/40 BTP
-6
400mil -6L -G6 -G6L TSOP-2
143MHz
7
Z2V56S20/30/40 BTP
-7
400mil -7L -G7 -G7L TSOP-2
133MHz
7.5
Z2V56S20/30/40 BTP
-75
400mil -75L -G75 -G75L TSOP-2
125MHz
8
Z2V56S20/30/40 BTP
-8
400mil -8L -G8 -G8L TSOP-2
Type Designation Code
Z2 V 56 S 3 0 B TP-G 7
Access Item
-6 : 6ns ( 166MHz/3-3-3) -7 : 7 ns (143MHz/3-3-3) -75 : 7.5ns ( 133MHz/3-3-3) -8 : 8 ns (100MHz/2-2-2)
Package Type Process Generation Function Organization Synchronous DRAM Density Interface Mezza DRAM
TP : TSOP(II); G: Pb Free B : 3rd generation 0 : Random Column 2 : x4, 3 :x8, 4: x16
56 :256Mbit V :LVTTL
Jan.2004
Rev.1.1
256Mb Synchronous DRAM :010-8287 3941/42/43/44 :010-8287 3945 http://www.echip.com.cn
256Mb Synchronous DRAMP2V56S20BTP(4-BANKx16,777,216-WORDx4-BIT) P2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) P2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT) Z2V56S30BTP (4-BANK x 8,388,6084-WORD x 8-BIT) Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are subject to change without notice.
DESCRIPTION
Z2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and Z2V56S30BTP is organized as 4-bank x 8,388,608-word x 8-bit and Z2V56S40BTP is organized as 4-bank x 4,194, 304-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
FEATURES
Z2V56S20BTP, Z2V56S30BTP and Z2V56S40BTP achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.
ITEM
tCLK Clock Cycle Time
(Min.)
CL=2 CL=3
Z2V56S20/30/40BTP
-6 -7 -75 -8
- - 10 10
6 7 7.5
8
tRAS Active to Precharge Command Period (Min.)
42 45
45 48
tRCD Row to Column Delay tAC Access Time from CLK tRC Ref /Active Command Period
(Min.) (Max.) (Min.)
CL=2 CL=3
15 20 --
20 6
5 5.4
5.4
60 63 67.5
20 6 6 70
V56S20 100 100
100
95
Icc1 Operation Current (Single Bank)
(Max.)
V56S30 110 110
110
100
V56S40 130 130
130
120
Icc6 Self Refresh Current
- Single 3.3V ±0.3V power supply
(Max.) -6,-7,-75,-8
3
3
3
3
- Max. Clock frequency:
-6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (P2V56S40BTP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9 , 11(x4) / A0-9(x8) / A0-8(x16)
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Unit ns ns ns ns ns ns ns mA
mA mA
mA
Jan.2004
Page -1
Rev.1.1
256Mb Synchronous DRAM :010-8287 3941/42/43/44 :010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT) Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
PIN CONFIGURATION (TOP VIEW)
Vdd Vdd NC DQ0 VddQ VddQ NC NC DQ0 DQ1 VssQ VssQ NC NC NC DQ2 VddQ VddQ NC NC DQ1 DQ3 VssQ VssQ NC NC Vdd Vdd NC NC /WE /WE /CAS /CAS /RAS /RAS /CS /CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 Vdd Vdd
Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0 BA1 A10/AP
A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
400mil x 875mil 54pin 0.8mm pitch TSOP(II)
X4 X8 X16
54 Vss
Vss
53 DQ15 DQ7
52 VssQ VssQ
51 DQ14 NC
50 DQ13 DQ6
49 VddQ VddQ
48 DQ12 NC
47 DQ11 DQ5
46 VssQ VssQ
45 DQ10 NC
44 DQ9 DQ4
43 VddQ VddQ
42 DQ8 NC
41 Vss
Vss
40 NC
NC
39 DQMU DQM
38 CLK
CLK
37 CKE CKE
36 A12
A12
35 A11
A11
34 A9
A9
33 A8
A8
32 A7
A7
31 A6
A6
30 A5
A5
29 A4
A4
28 Vss
Vss
Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
CLK CKE /CS /RAS /CAS /WE DQ0-15
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12
: Address I.