TOSHIBA CONFIDENTIAL TH58NVG7D2GTA20
AC TEST CONDITIONS
2.7 V VCC 3.6 V
Input pulse rise and fall time
0 V to VCC
Input comparison level
Output data comparison level
CL (50 pF) 1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (8) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta 0 to 70℃, VCC 2.7 V to 3.6 V)
Average Programming Time
Data Cache Busy Time in Write Cache (following 11h)
Data Cache Busy Time in Write Cache (following 15h)
Number of Partial Program Cycles in the Same Page
Block Erasing Time
(1) Refer to Application Note (11) toward the end of this document.
(2) tDCBSYW2 depends on the timing between internal programming time and data in time.
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend
on tRHOH (25 ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend
on tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE, ALE, /CE
or falling edge of /WE, and waveforms look like Extended Data Output Mode.