Document
TOSHIBA CONFIDENTIAL TH58NVG7D2GTA20
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128 GBIT (8G 8 BIT 2) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TH58NVG7D2G is a single 3.3 V 128 Gbit (149,189,296,128 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (8192 + 640) bytes 256 pages 8248 blocks. The device has two 8832-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 8832-byte increments. The Erase operation is implemented in a single block unit (2 Mbytes 160 Kbytes: 8832 bytes 256 pages).
The TH58NVG7D2G is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array Register Page size Block size
TH58NVG7D2G 8832 512K 8 2 8832 8 8832 bytes (2M 160 K) bytes
Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control Serial input/output
Command control
Number of valid blocks Min 7992 blocks Max 8248 blocks
Power supply VCC 2.7 V to 3.6 V
Access time
Cell array to register 200 s max
Serial Read Cycle
25 ns min
Program/Erase time Auto Page Program
Auto Block Erase
1400 s/page typ. 5 ms/block typ.
Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby
TBD ( 30 mA max.) per 1chip TBD ( 30 mA max.) per 1chip TBD ( 30 mA max.) per 1chip
100 A max
Package (Weight: TBD g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (16).
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TOSHIBA CONFIDENTIAL
PIN ASSIGNMENT (TOP VIEW)
TH58NVG7D2GTA20
PIN NAMES
8
Vcc Vss NC NC NC RY / BY 2 RY / BY 1 RE CE 1 CE 2 NC VCC VSS NC NC CLE ALE WE WP NC NC NC Vss Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TH58NVG7D2GTA20
8
48 Vss 47 NC 46 NC 45 NC 44 I/O8 43 I/O7 42 I/O6 41 I/O5 40 NC 39 NC 38 Vcc 37 VCC 36 VSS 35 NC 34 Vcc 33 NC 32 I/O4 31 I/O3 30 I/O2 29 I/O1 28 NC 27 NC 26 NC 25 Vss
I/O1 ~ I/O8 CE 1 CE 2 WE RE CLE ALE WP
RY/BY 1 RY/BY 2
VCC VSS N.C
I/O port Chip enable (Chip A) Chip enable (Chip B) Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy (Chip A) Ready/Busy (Chip B) Power supply Ground No connection
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BLOCK DIAGRAM
TOSHIBA CONFIDENTIAL TH58NVG7D2GTA20
I/O1 to I/O8 CE 1 CLE ALE WE RE WP PSL RY / BY 1
CE 2
I/O Control circuit
(Chip A) Status register Address register
Command register
Logic control
Control circuit
VCC
VSS
Column buffer Column decoder
Data register Sense .