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ESD7421N2T5G Dataheets PDF



Part Number ESD7421N2T5G
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description ESD Protection Diodes
Datasheet ESD7421N2T5G DatasheetESD7421N2T5G Datasheet (PDF)

ESD7421, SZESD7421 ESD Protection Diodes Micro−Packaged Diodes for ESD Protection The ESD7421 is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, automotive sensors, infotainment, MP3 players, digital cameras and many other applications where board space comes at a premium. Specificat.

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ESD7421, SZESD7421 ESD Protection Diodes Micro−Packaged Diodes for ESD Protection The ESD7421 is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, automotive sensors, infotainment, MP3 players, digital cameras and many other applications where board space comes at a premium. Specification Features • Low Capacitance 0.3 pF • Low Clamping Voltage • Low Leakage 100 nA • Response Time is < 1 ns • IEC61000−4−2 Level 4 ESD Protection • SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS Rating Symbol Value Unit IEC 61000−4−2 (ESD) Contact Air ±12 kV ±15 Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient Junction and Storage Temperature Range Lead Solder Temperature − Maximum (10 Second Duration) °PD° RqJA TJ, Tstg TL 300 mW 400 °C/W −55 to +150 °C 260 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0 x 0.75 x 0.62 in. http://onsemi.com Pin 1 Pin 2 MARKING DIAGRAM XDFN2 (SOD−882) CASE 711AM 5M G 5 = Specific Device Code M = Date Code G = Pb−Free Package ORDERING INFORMATION Device ESD7421N2T5G Package XDFN2 (Pb−Free) Shipping† 8000 / Tape & Reel SZESD7421N2T5G XDFN2 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2014 July, 2014 − Rev. 1 1 Publication Order Number: ESD7421/D ESD7421, SZESD7421 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM Working Peak Reverse Voltage IR Maximum Reverse Leakage Current @ VRWM VBR1 Breakdown Voltage @ IT VBR2 Breakdown Voltage @ IT IT Test Current *See Application Note AND8308/D for detailed explanations of datasheet parameters. I IPP IT VC VBR2 VRWM IR IIRT VRWM VBR1 VC V IPP Bi−Directional TVS ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage VRWM Pin 1 to GND Pin 2 to GND 5 16 V 5 10 Breakdown Voltage Breakdown Voltage Reverse Leakage Current VBR1 VBR2 IR IT = 1 mA, Pin 1 to GND IT = 1 mA, Pin 2 to GND VRWM = 5 V, I/O Pin to GND 16.5 10.5 100 V 14 V 500 nA Clamping Voltage (Note 2) VC IEC61000−4−2, ±8 kV Contact See Figures 2 and 3 Clamping Voltage TLP (Note 3) VC IPP = 8 A IPP = 16 A IPP = −8 A IPP = −16 A 35 38.1 −21 −29.5 V Junction Capacitance CJ VR = 0 V, f = 1 MHz between I/O Pins and GND 0.3 0.6 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. For test procedure see Figure 5 and application note AND8307/D. 3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns. http://onsemi.com 2 ESD7421, SZESD7421 CAPACITANCE (pF) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −5 −4 −3 −2 −1 0 1 2 3 4 VBias (V) Figure 1. Typical CV Characteristic Curve Pin1 to GND (GND connected to Pin2) 5 120 20 100 0 80 −20 60 −40 40 −60 20 −80 0 −100 −20 −25 0 −120 25 50 75 100 125 150 −25 0 25 50 75 100 125 150 TIME (ns) TIME (ns) Figure 2. IEC61000−4−2 +8 kV Contact ESD Clamping Voltage Pin1 to GND (GND connected to Pin2) Figure 3. IEC61000−4−2 −8 kV Contact ESD Clamping Voltage Pin1 to GND (GND connected to Pin2) VOLTAGE (V) VOLTAGE (V) http://onsemi.com 3 ESD7421, SZESD7421 IEC 61000−4−2 Spec. Level First Peak Test Volt- Current Current at age (kV) (A) 30 ns (A) 1 2 7.5 4 2 4 15 8 3 6 22.5 12 48 30 16 Current at 60 ns (A) 2 4 6 8 IEC61000−4−2 Waveform Ipeak 100% 90% I @ 30 ns I @ 60 ns 10% Figure 4. IEC61000−4−2 Spec tP = 0.7 ns to 1 ns ESD Gun TVS Oscilloscope 50 W Cable 50 W Figure 5. Diagram of ESD Clamping Voltage Test Setup The following is taken from Application Note AND8308/D − Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during.


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