MSC8144E

Freescale Semiconductor Data Sheet: Document Number: MSC8144E Rev. 14, 5/2010 MSC8144E Quad Core Digital Signal Processor FC-PBGA–783 29 mm × 29 mm Four StarCore® SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes. Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets. 128 Kbyte L2 shared instruction cache. 512 Kbyte M2 memory for critical data and temporary data buffering. 10 Mbyte 128-bit wide M3 memory. 96 Kbyte boot ROM. Three input clocks (shared, global, and differential). Four PLLs (system, core, global, and serial RapidIO). Security Engine (SEC0 optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP using 4 crypto-channels with multi-command chains, integrated controller for assignment of the six execution units (PKEU, DEU, AESU, AFEU, MDEU, and KEU0) and the random number generator (RNG), and XOR engine to accelerate parity checking for RAID storage applications. DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 ...