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XE8805A Dataheets PDF



Part Number XE8805A
Manufacturers Semtech
Logo Semtech
Description Sensing Machine Data Acquisition MCU
Datasheet XE8805A DatasheetXE8805A Datasheet (PDF)

XE8805/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs NotNeRwecDoesmigmnesnded for XE8805/05A – SX8805R Sensing Machine – Data Acquisition with 16+10 bit ZoomingADC™ and buffered DACs General Description The XE8805A is a data acquisition ultra lowpower low-voltage system on a chip (SoC) with a high efficiency microcontroller unit embedded (MCU), allowing for 1 MIPS at 300uA and 2.4 V, and multiplying in one clock cycle. The XE8805A includes a high resolution acquisition pa.

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XE8805/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs NotNeRwecDoesmigmnesnded for XE8805/05A – SX8805R Sensing Machine – Data Acquisition with 16+10 bit ZoomingADC™ and buffered DACs General Description The XE8805A is a data acquisition ultra lowpower low-voltage system on a chip (SoC) with a high efficiency microcontroller unit embedded (MCU), allowing for 1 MIPS at 300uA and 2.4 V, and multiplying in one clock cycle. The XE8805A includes a high resolution acquisition path with the 16+10 bits ZoomingADC and two buffered DACs. The XE8805A is available with on chip ROM (the SX8805) or Multiple-Time-Programmable (MTP) program memory. Applications • Portable, battery operated instruments • Current loop powered instruments • Wheatstone bridge interfaces • Pressure and chemical sensors • HVAC control • Metering • Sports watches, wrist instruments Key product Features • Low-power, high resolution ZoomingADC • 0.5 to 1000 gain with offset cancellation • up to 16 bits analog to digital converter • up to 13 inputs multiplexer • Low-voltage low-power controller operation • 2 MIPS with 2.4 V to 5.5 V operation • 300 µA at 1 MIPS over voltage range • 22 kByte (8 kInstruction) MTP • 520 Byte RAM data memory • RC and crystal oscillators • 5 reset, 22 interrupt, 8 event sources • 8 bit and 16 bit buffered DACs • 100 years MTP Flash retention at 55°C Ordering Information Product Temperature range Memory type XE8805MI028* -40°C to 85 °C MTP XE8805AMI000 -40°C to 85 °C MTP XE8805AMI028LF -40°C to 85 °C MTP SX8805Rxxx -40°C to 85 °C** ROM *Not for new designs **Extended temperature range on request Package LQFP64 die LQFP64 Rev 1 January 2006 www.semtech.com XE8805/05A Sensing Machine Data Acquisition MCU with Zooming ADC and DACs TABLE OF CONTENTS Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22 XE8805/05A Overview XE8805/05A Performance XE8805/05A CPU XE8805/05A Memory System Block Reset generator Clock generation Interrupt handler Event handler Low power RAM Port A Port B Port C Universal Asynchronous Receiver/Transmitter (UART) Universal Synchronous Receiver/Transmitter (USRT) Acquisition Chain (ZoomingADC™) Voltage multiplier Signal D/A (DAS) Bias D/A (DAB) Counters/Timers/PWM The Voltage Level Detector XE8805/05A Dimensions NotNeRwecDoesmigmnesnded for © Semtech 2006 www.semtech.com 1. General Overview CONTENTS 1.1 1.1.1 1.1.2 Top schematic General description XE8805 vs XE8805A 1.2 1.2.1 1.2.2 Pin map Bare die LQFP-64 1.3 Pin assignment XE8805/05A 1-2 1-2 1-4 1-4 1-4 1-5 1-6 NotNeRwecDoesmigmnesnded for © Semtech 2006 www.semtech.com 1-1 NotNeRwecDoesmigmnesnded for XE8805/05A 1.1 Top schematic 1.1.1 General description The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the Coolrisc816® CPU core. This core includes an 8x8 multiplier and 16 internal registers. The bus controller generates all control signals for access to all data registers other than the CPU internal registers. The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained in its control registers. Possible reset sources are the power-on-reset (POR), the external pin RESET, the watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. Different low power modes are implemented. The clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal oscillator (XTAL) or an external clock source (given on the OSCIN pin). The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8 low power data registers. If power consumption is important for the application, the variables that need to be accessed very often should be stored in these registers rather than in the RAM. The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt source is active. Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e. the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt source is active. The Port B is an 8 bit parallel IO port with analog capabilities. The URST, UART, and PWM block also make use of this port. The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit versi.


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