Document
Pm25LQ032C
FEATURES
• Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V
• Memory Organization - Pm25LQ032C: 4096K x 8 (32 Mbit)
• Cost Effective Sector/Block Architecture - 32Mb : Uniform 4KByte sectors / sixty-four uniform
64KByte blocks
• Serial Peripheral Interface (SPI) Compatible - Supports single-, dual- or quad-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 104 MHz clock rate for fast read - Maximum 208MHz clock rate equivalent Dual SPI - Maximum 400MHz clock rate equivalent Quad SPI • Byte Program Operation - Typical 8 us/Byte • Page Program (up to 256 Bytes) Operation - Typical 1 ms per page program
• Sector, Block or Chip Erase Operation - Sector Erase (4KB) 50ms (Typ) - Block Erase (64KB) 500ms (Typ) - Chip Erase 15S (32Mb) •Deep power-down mode 1uA (Typ) Security protect function - sector unlock (Appendix 1)
32Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface
• Low Power Consumption - Max 15 mA active read current - Max 20 mA program/erase current - Max 30uA standby current
• Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin
• Software Write Protection - The Block Protect (BP3, BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only
• High Product Endurance - Guaranteed 100,000 program/erase cycles per single sector - Minimum 20 years data retention
• Industrial Standard Pin-out and Package - 8-pin 208mil SOIC - 8-contact WSON - 16-pin 300mil SOP - 8-pin 208mil VSOP - Lead-free (Pb-free), halogen-free package
Additional 64-byte Security information one-time programmable (OTP) area
GENERAL DESCRIPTION
The Pm25LQ032C are 32 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad-output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers.
The Pm25LQ032C are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks.
The Pm25LQ032C are manufactured on pFLASH™’s advanced non-volatile technology. The devices are offered in 8-pin SOIC 208mil and 8-contact WSON.
Chingis Technology Corp.
1
Date February. 2012, Rev: 1.6.1
PRODUCT ORDERING INFORMATION
Pm25LQxxx - B C E
Pm25LQ032C
Environmental Attribute E = Lead-free (Pb-free) package
Temperature Range C = Commercial Grade (-40°C to +125°C)
Package Type B = 8-pin SOIC 208 mil (8B) K = 8-contact WSON (8K) M= 16-pin SOIC 300mil (8M) P= PDIP F= 8-pin VSOP 208 mil (8F) pFlash Device Number Pm25Q032C
Part Number
Operating Frequency (MHz) Package
Temperature Range
Pm25LQ032C-BCE
104
8B 208mil SOIC
Pm25LQ032C-KCE Pm25LQ032C-PCE Pm25LQ032C-MCE
104
8Q WSON
104
8P Commercial Grade 300mil PDIP (-40oC to +125oC)
104
8M 300mil SOIC
Pm25LQ032C-FCE
104
8F 208mil VSOP
Chingis Technology Corp.
2
Date February. 2012, Rev: 1.6.1
CONNECTION DIAGRAMS
CE# 1
8
SO (IO1)
2
7
WP# (IO2)
3
6
GND
4
5
Vcc CE# 1
HOLD# (IO3) SO (IO1) 2
WP# (IO2) 3
SCK
GND 4
SI (IO0)
Pm25LQ032C
8 Vcc 7 HOLD#(IO3) 6 SCK 5 SI (IO0)
8-Pin SOIC/VSOP
8-Contact WSON
CE# SO(IO1)
WP#(IO2)
GND
1 2 3 4
8 7 6 5
8-Pin PDIP
Vcc HNOCL(IDO#3()IO3)
SCK SI(IO0)
16-Pin SOIC
Chingis Technology Corp.
3
Date February. 2012, Rev: 1.6.1
Pm25LQ032C
PIN DESCRIPTIONS
SYMBOL TYPE
DESCRIPTION
CE#
SCK SI (IO0) SO (IO1) GND Vcc WP# (IO2)
HOLD# (IO3)
INPUT
INPUT INPUT/OUTPUT INPUT/OUTPUT INPUT/OUTPUT
INPUT/OUTPUT
Chip Enable: CE# low activates the devices internal circuitries for device operation. CE# high deselects the devices and switches into standby mode to reduce the power consumption. When a device is not selected, data will not be accepted via the serial input pin (Sl), and the serial output pin (SO) will remain in a high impedance state. Serial Data Clock Serial Data Input/Output Serial Data Input/Output
Ground Device Power Supply
Write Protect/Serial Data Output: A hardware program/erase protection for all or part of a memory array. When the WP# pin is low, memory array write-protection depends on the setting of BP3, BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the status register are not write-protected. When the QE bit of is set “1”, the /WP pin (Hardware Write Protect) function is not available since this pin is used for IO2
Hold: Pause serial communication by the master device without resetting the serial sequence..