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Y60NM60 Dataheets PDF



Part Number Y60NM60
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description STY60NM60
Datasheet Y60NM60 DatasheetY60NM60 Datasheet (PDF)

STY60NM60 N-CHANNEL 600V - 0.050Ω - 60A Max247 Zener-Protected MDmesh™Power MOSFET TYPE VDSS RDS(on) ID STY60NM60 600V < 0.055Ω 60 A TYPICAL RDS(on) = 0.050Ω HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL INDUSTRY’S LOWEST ON-RESISTANCE DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layou.

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STY60NM60 N-CHANNEL 600V - 0.050Ω - 60A Max247 Zener-Protected MDmesh™Power MOSFET TYPE VDSS RDS(on) ID STY60NM60 600V < 0.055Ω 60 A TYPICAL RDS(on) = 0.050Ω HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL INDUSTRY’S LOWEST ON-RESISTANCE DESCRIPTION The MDmesh™ is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company’s PowerMESH™ horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company’s proprietary strip technique yields overall dynamic performance that is significantly better than that of similar competition’s products. APPLICATIONS The MDmesh™ family is very suitable for increasing power density of high voltage converters allowing system miniaturization and higher efficiencies. 3 2 1 Max247 INTERNAL SCHEMATIC DIAGRAM ORDERING INFORMATION SALES TYPE MARKING STY60NM60 Y60NM60 PACKAGE Max247 PACKAGING TUBE July 2003 1/8 STY60NM60 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDS Drain-source Voltage (VGS = 0) VDGR Drain-gate Voltage (RGS = 20 kΩ) VGS Gate- source Voltage ID Drain Current (continuous) at TC = 25°C ID Drain Current (continuous) at TC = 100°C IDM ( ) Drain Current (pulsed) PTOT Total Dissipation at TC = 25°C VESD(G-S) Gate source ESD(HBM-C=100pF, R=15KΩ) Derating Factor dv/dt (1) Peak Diode Recovery voltage slope Tstg Storage Temperature Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area (1) ISD ≤60A, di/dt ≤400 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Thermal Resistance Junction-ambient Max Tl Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) Value 600 600 ±30 60 37.8 240 560 6 4.5 15 –65 to 150 150 0.22 30 300 Max Value 30 1.4 Unit V V V A A A W KV W/°C V/ns °C °C °C/W °C/W °C Unit A J GATE-SOURCE ZENER DIODE Symbol Parameter BVGSO Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/8 STY60NM60 ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 600 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125°C 10 100 IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 345 RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 30 A 0.050 0.055 Unit V µA µA µA V Ω DYNAMIC Symbol gfs (1) Parameter Forward Transconductance Ciss Coss Crss RG Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance Test Conditions VDS = ID(on) x RDS(on)max, ID = 30 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Typ. 35 7300 2000 40 1.8 Max. Unit S pF pF pF Ω SWITCHING ON Symbol Parameter td(on) tr Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions VDD = 300 V, ID = 30 A RG = 4.7Ω VGS = 10 V (see test circuit, Figure 3) VDD = 470 V, ID = 60 A, VGS = 10 V Min. Typ. 55 95 Max. Unit ns ns 178 266 44.5 95 nC nC nC SWITCHING OFF Symbol Parameter tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400 V, ID = 60 A, RG = 4.7Ω, VGS = 10 V (see test circuit, Figure 5) Min. Typ. 130 76 105 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 60 A, VGS = 0 trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 60 A, di/dt = 100 A/µs, VDD = 30 V, Tj = 150°C (see test circuit, Figure 5) Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Min. Typ. 600 14 48 Max. 60 240 1.5 Unit A A V ns µC A 3/8 STY60NM60 Safe Operating Area Thermal Impedance Output Characteristics Transfer Characteristics Transconductance Sta.


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